公开(公告)号：US12062615B2

公开(公告)日：2024-08-13

申请号：US18164626

申请日：2023-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

公开(公告)号：US09748332B1

公开(公告)日：2017-08-29

申请号：US15374515

申请日：2016-12-09

Applicant: Macronix International Co., Ltd.

Inventor： Chih Kai Yang ,  Chen Yu Cheng ,  Shih Chin Lee ,  Ching Hung Wang ,  Tzung-Ting Han

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11521

CPC classification number: H01L29/0649 ,  H01L21/7682 ,  H01L27/11524 ,  H01L29/7883

Abstract: A semiconductor device includes a semiconductor substrate, multiple memory cells on the semiconductor substrate arranged along a first dimension and along a second dimension that is orthogonal to the first dimension, in which each memory cell of the multiple memory cells includes a channel region in the semiconductor substrate, a tunnel dielectric layer on the channel region, and a first electrode layer on the tunnel dielectric layer. Along the first dimension, the channel region of each memory cell of the multiple memory cells is separated from the channel region of an adjacent memory cell of the multiple memory cells by a corresponding first air gap, each first air gap extending from below an upper surface of the semiconductor substrate up to an inter-electrode dielectric layer.

公开(公告)号：US20230187359A1

公开(公告)日：2023-06-15

申请号：US18164626

申请日：2023-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76895 ,  H01L21/76805 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

公开(公告)号：US20220173040A1

公开(公告)日：2022-06-02

申请号：US17109960

申请日：2020-12-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

公开(公告)号：US11610842B2

公开(公告)日：2023-03-21

申请号：US17109960

申请日：2020-12-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.