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公开(公告)号：US20150063023A1
公开(公告)日：2015-03-05
申请号：US14535042
申请日：2014-11-06
Applicant: Macronix International Co., Ltd.
Inventor： Tzung Shen Chen , Shuo Nan Hong , Yi Ching Liu , Chun-Hsiung Hung
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3422 , G11C16/3427 , G11C16/3431
Abstract: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.
Abstract translation: 集成电路器件包括半导体衬底，衬底上的第一存储器块，包括NAND存储器单元，在衬底上的第二存储器块，包括NAND存储器单元，以及控制器电路。 第一和第二存储器块可配置为响应于第一操作算法存储用于第一数据使用模式的数据以读取，编程和擦除数据，以及响应于第二操作算法读取数据使用的第二模式 ，分别编程和擦除数据。 控制器电路耦合到第一和第二存储器块，并且被配置为执行第一和第二操作算法，其中在第一操作算法中应用的读操作的字线通过电压处于比第二字的较低电压电平 用于在第二操作算法中应用的读操作的线通电压。
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公开(公告)号：US09412460B2
公开(公告)日：2016-08-09
申请号：US14535042
申请日：2014-11-06
Applicant: Macronix International Co., Ltd.
Inventor： Tzung Shen Chen , Shuo Nan Hong , Yi Ching Liu , Chun-Hsiung Hung
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3422 , G11C16/3427 , G11C16/3431
Abstract: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.
Abstract translation: 集成电路器件包括半导体衬底，衬底上的第一存储器块，包括NAND存储器单元，在衬底上的第二存储器块，包括NAND存储器单元，以及控制器电路。 第一和第二存储器块可配置为响应于第一操作算法存储用于第一数据使用模式的数据以读取，编程和擦除数据，以及响应于第二操作算法读取数据使用的第二模式 ，分别编程和擦除数据。 控制器电路耦合到第一和第二存储器块，并且被配置为执行第一和第二操作算法，其中在第一操作算法中应用的读操作的字线通过电压处于比第二字的较低电压电平 用于在第二操作算法中应用的读操作的线通电压。
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公开(公告)号：US10755790B2
公开(公告)日：2020-08-25
申请号：US16254933
申请日：2019-01-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Teng-Hao Yeh , Yi Ching Liu
Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.
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