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公开(公告)号：US08161422B2
公开(公告)日：2012-04-17
申请号：US12349108
申请日：2009-01-06
IPC分类号： G06F17/50
摘要： A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.
摘要翻译： 提供了一种用于在用于制造半导体集成电路的光掩模的设计中对光刻工艺进行建模的方法，更具体地说，用于模拟中间范围闪光效应。 对于当点扩散函数具有根据预定标准缓慢变化的斜率时，从约5λ/ NA的第一ROI1到距离ROI2的影响区域（ROI），则至少在从ROI1到ROI2的距离范围内的掩模形状 在计算SOCS卷积之前进行平滑处理。 该方法提供了一种用于以足够的精度模拟中等范围闪光效果的快速方法。
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2.发明申请公开(公告)号：US20100175043A1
公开(公告)日：2010-07-08
申请号：US12349108
申请日：2009-01-06
IPC分类号： G06F17/50
摘要： A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROI1 to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.
摘要翻译： 提供了一种用于在用于制造半导体集成电路的光掩模的设计中对光刻工艺进行建模的方法，更具体地说，用于模拟中间范围闪光效应。 对于当点扩散函数具有根据预定标准缓慢变化的斜率时，从约5λ/ NA的第一ROI1到距离ROI2的影响区域（ROI），则至少在从ROI1到ROI2的距离范围内的掩模形状 在计算SOCS卷积之前进行平滑处理。 该方法提供了一种用于以足够的精度模拟中等范围闪光效果的快速方法。
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公开(公告)号：US07343582B2
公开(公告)日：2008-03-11
申请号：US11138172
申请日：2005-05-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G03F7/70441 , G06F2217/12 , Y02P90/265
摘要： A method, program product and system is disclosed for performing optical proximity correction (OPC) wherein mask shapes are fragmented based on the effective image processing influence of neighboring shapes on the shape to be fragmented. Neighboring shapes are smoothed prior to determining their influence on the fragmentation of the shape of interest, where the amount of smoothing of a neighboring shape increases as the influence of the neighboring shape on the image process of the shape of interest decreases. A preferred embodiment includes the use of multiple regions of interactions (ROIs) around the shape of interest, and assigning a smoothing parameter to a given ROI that increases as the influence of shapes in that ROI decreases with respect to the shape to be fragmented. The invention provides for accurate OPC that is also efficient.
摘要翻译： 公开了一种用于执行光学邻近校正（OPC）的方法，程序产品和系统，其中基于相邻形状对要分段的形状的有效图像处理影响，掩模形状被分段。 相邻形状在确定其对感兴趣的形状的碎片的影响之前被平滑，其中相邻形状的平滑化量随着相关形状对感兴趣形状的图像处理的影响而增加。 优选实施例包括使用感兴趣的形状周围的多个交互区域（ROI），以及为给定的ROI分配平滑参数，随着该ROI中的形状的影响相对于待分割的形状而减小。 本发明提供了也是有效的精确OPC。
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4.发明授权Verifying mask layout printability using simulation with adjustable accuracy 失效使用可调精度的模拟验证面具布局的可印刷性公开(公告)号：US07565633B2
公开(公告)日：2009-07-21
申请号：US11619320
申请日：2007-01-03
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy simulated image. Where the lower accuracy simulated image is determined as potentially including an error, a further simulation of the designated portion of the mask layout with a higher accuracy will be performed.
摘要翻译： 公开了一种用于验证光刻工艺的掩模布局的可印刷性的方法，系统和计算机程序产品。 使用精度较低的掩模布局的简化版本来模拟设计的掩模布局的光刻工艺的模拟，以产生较低精度的模拟图像。 在将低精度模拟图像确定为潜在地包括错误的情况下，将执行具有更高精度的掩模布局的指定部分的进一步模拟。
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5.发明申请公开(公告)号：US20090125868A1
公开(公告)日：2009-05-14
申请号：US12357648
申请日：2009-01-22
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
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6.发明授权System and method of smoothing mask shapes for improved placement of sub-resolution assist features 失效平滑掩模形状的系统和方法，以改进子分辨率辅助特征的放置公开(公告)号：US07261981B2
公开(公告)日：2007-08-28
申请号：US10707778
申请日：2004-01-12
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.
摘要翻译： 公开了一种相对于掩模的预定主要形状提供光刻掩模的相关形状的方法。 该方法包括从掩模的预定主要形状生成简化的布局图案。 通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。 然后相对于简化的掩模图案生成相关联的形状。
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公开(公告)号：US08214770B2
公开(公告)日：2012-07-03
申请号：US12357648
申请日：2009-01-22
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
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公开(公告)号：US07503028B2
公开(公告)日：2009-03-10
申请号：US11306750
申请日：2006-01-10
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
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9.发明申请公开(公告)号：US20080163153A1
公开(公告)日：2008-07-03
申请号：US11619320
申请日：2007-01-03
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy simulated image. Where the lower accuracy simulated image is determined as potentially including an error, a further simulation of the designated portion of the mask layout with a higher accuracy will be performed.
摘要翻译： 公开了一种用于验证光刻工艺的掩模布局的可印刷性的方法，系统和计算机程序产品。 使用精度较低的掩模布局的简化版本来模拟设计的掩模布局的光刻工艺的模拟，以产生较低精度的模拟图像。 在将低精度模拟图像确定为潜在地包括错误的情况下，将执行具有更高精度的掩模布局的指定部分的进一步模拟。
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公开(公告)号：US07642020B2
公开(公告)日：2010-01-05
申请号：US11465227
申请日：2006-08-17
申请人： Geng Han , Scott M. Mansfield
发明人： Geng Han , Scott M. Mansfield
IPC分类号： G03F9/00
CPC分类号： G03F7/70441 , G03F7/705
摘要： A methodology to improve the through-process model calibration accuracy of a semiconductor manufacturing process using lithographic methods by setting the correct defocus and image plane position in a patterning process model build. Separations of the optical model and the photoresist model are employed by separating out the adverse effects of the exposure tool from the effects of the photoresist. The exposure tool is adjusted to compensate for the errors. The methodology includes a determination of where the simulator best focus location is in comparison to the empirically derived best focus location.
摘要翻译： 一种通过在图案化过程模型构建中设置正确的散焦和图像平面位置来改进使用光刻方法的半导体制造工艺的过程模型校准精度的方法。 通过将曝光工具的不利影响与光致抗蚀剂的作用分离，可采用光学模型和光致抗蚀剂模型的分离。 调整曝光工具以补偿错误。 该方法包括确定模拟器最佳聚焦位置与经验派生的最佳聚焦位置相比较的位置。
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