公开(公告)号：US06274457B1

公开(公告)日：2001-08-14

申请号：US09481386

申请日：2000-01-12

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1

摘要翻译： 一种半导体器件，包括半导体衬底，形成在衬底中并具有包括侧壁和底表面的内壁的沟槽，沉积在内壁上的氧化硅膜和沉积在氧化硅膜上的掩埋氧化膜以埋入 沟槽，其中侧壁具有从基板的表面到沟槽的底表面以第一轮廓角A1倾斜的侧壁的第二轮廓角A2和第三轮廓角A3，并且轮廓角具有 A1

公开(公告)号：US06268263B1

公开(公告)日：2001-07-31

申请号：US09196134

申请日：1998-11-20

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L2176

CPC分类号： H01L21/31053 ,  H01L21/76224 ,  Y10S438/97

摘要： A trench (21) is formed in a silicon substrate (1) on which an underlying oxide film (2) and a silicon nitride film (3) are formed. Then, a silicon oxide (11) is deposited by an HDP-CVD method to fill the trench (21) with the oxide. Further, a resist (41) including a second resist portion (42), and a resist (43) are formed. The silicon oxide film (11) that is not covered with the resists (41) and (43), is removed by dry etching. Etch selectivity of the silicon oxide film (11) to the stopper film (3) is not less than a value (2(c−a)/d) obtained by dividing twice a value (c−a) which is obtained by subtracting an alignment margin (a) from the maximum film thickness (c) of the silicon oxide film (11), by the film thickness (d) of the stopper film (3). The resists (41) and (43) are then removed, and the residual silicon oxide film (11B, 11DC, 11DE, 11FE) is polished and removed by the CMP method. This forms a trench type element isolation with no depression at its edge portion.

摘要翻译： 在其上形成有下面的氧化膜（2）和氮化硅膜（3）的硅衬底（1）中形成沟槽（21）。 然后，通过HDP-CVD法沉积氧化硅（11）以用氧化物填充沟槽（21）。 此外，形成包括第二抗蚀剂部分（42）和抗蚀剂（43）的抗蚀剂（41）。 通过干蚀刻除去未被抗蚀剂（41）和（43）覆盖的氧化硅膜（11）。 氧化硅膜（11）对阻挡膜（3）的蚀刻选择性不小于通过将通过减去取向余量（a）获得的值（ca）的两倍所获得的值（2（ca）/ d） ）从氧化硅膜（11）的最大膜厚度（c）到阻挡膜（3）的膜厚度（d）。 然后除去抗蚀剂（41）和（43），并通过CMP方法研磨和除去残留氧化硅膜（11B，11DC，11DE，11FE）。 这形成了在其边缘部分没有凹陷的沟槽型元件隔离。

公开(公告)号：US6150233A

公开(公告)日：2000-11-21

申请号：US118925

申请日：1998-07-20

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Maiko Sakai ,  Hiromichi Kobayashi

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Maiko Sakai ,  Hiromichi Kobayashi

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76232 ,  Y10S148/05

摘要： An underlaid silicon oxide film (2) and a polycrystalline silicon film (5) are formed in this order on a surface (1S) of a silicon substrate (1). The polycrystalline silicon film (5) and the underlaid silicon oxide (2) are opened by anisotropic etching, to form a trench (21) extending to the inside of the semiconductor substrate (1). A silicon oxide film (11) formed by HDP-CVD is buried in the trench (21). A resist (41) is formed only on a surface of the silicon oxide film (11) in a device isolation region (20). The silicon oxide film (11) in an active region (30) is removed by dry etching with the resist (41) as a mask. After removing the resist (41), only the polycrystalline silicon film (5) is removed by dry etching. The underlaid oxide film (2) is removed by wet etching with hydrofluoric acid. By this method of manufacturing a semiconductor device, the surface of the semiconductor substrate and a trench-type device isolation are flattened effectively at low cost.

摘要翻译： 依次在硅基板（1）的表面（1S）上形成底层氧化硅膜（2）和多晶硅膜（5）。 通过各向异性蚀刻打开多晶硅膜（5）和底层氧化硅（2），形成延伸到半导体衬底（1）内部的沟槽（21）。 通过HDP-CVD形成的氧化硅膜（11）被埋在沟槽（21）中。 在器件隔离区域（20）中仅在氧化硅膜（11）的表面上形成抗蚀剂（41）。 通过用抗蚀剂（41）作为掩模的干蚀刻除去活性区域（30）中的氧化硅膜（11）。 除去抗蚀剂（41）后，通过干蚀刻除去多晶硅膜（5）。 通过用氢氟酸湿蚀刻除去底层氧化物膜（2）。 通过这种制造半导体器件的方法，半导体衬底的表面和沟槽型器件隔离以低成本被有效地扁平化。

公开(公告)号：US06372604B1

公开(公告)日：2002-04-16

申请号：US09860505

申请日：2001-05-21

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： There is provided a method for forming a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than the CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

摘要翻译： 提供了一种形成沟槽型元件隔离结构的方法，其中在沟槽型元件隔离的嵌入式氧化物膜的边缘部分中不形成凹坑。不仅仅在CVD膜上形成具有比CVD膜更高的耐蚀刻性的热氧化膜 嵌入的氧化膜的周围形成在硅基板上的槽内，而且在从硅衬底表面向上突出的嵌入氧化膜的侧面上。

公开(公告)号：US06265743B1

公开(公告)日：2001-07-24

申请号：US08963764

申请日：1997-11-04

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L27108

CPC分类号： H01L21/76232

摘要： There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than a CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

摘要翻译： 提供了沟槽型元件隔离结构，其中在沟槽型元件隔离的嵌入式氧化物膜的边缘部分中不形成凹陷。 不仅在形成于硅基板上的槽内的嵌入氧化膜的周围，而且在从硅衬底表面向上突出的嵌入氧化膜的侧面上形成具有比CVD膜更高的耐蚀刻性的热氧化膜。

公开(公告)号：US5889335A

公开(公告)日：1999-03-30

申请号：US28112

申请日：1998-02-23

申请人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

发明人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

IPC分类号： H01L21/76 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L21/383

CPC分类号： H01L23/544 ,  H01L21/0274 ,  H01L21/32139 ,  H01L21/76229 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

摘要翻译： 本发明提供一种半导体器件，其包括沟槽型元件隔离，其在不劣化器件能力的情况下进行精确对准，以及制造这种半导体器件的方法。 由于在沟槽（10A）的边缘邻近区域中形成虚拟栅电极（14A），所以实现了不产生蚀刻余量的结构。 此外，由于在虚拟栅极电极（14A）的表面上设置高差，使得高度差反映了氧化硅膜（2A）的表面和硅表面之间的预备高度差 基板（1），可以使用伪栅电极本身（14A）作为对准标记。

公开(公告)号：US06323102B1

公开(公告)日：2001-11-27

申请号：US09090422

申请日：1998-06-04

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Maiko Sakai

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Maiko Sakai

IPC分类号： H01L2176

CPC分类号： H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L21/76232

摘要： A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a satisfactory shape is obtainable.

摘要翻译： 一种制造半导体器件的方法，其具有通过HDP-CVD方法嵌入绝缘膜的具有微连接沟槽隔离的半导体器件，包括：通过相对于表面上层压的绝缘膜选择性地进行干蚀刻来进行预平面化的步骤 作为活性区域的基板，以及通过CMP方法进行研磨以提高绝缘膜的表面平坦性的步骤，其中在开口沟槽部分时使用的蚀刻掩模具有多层结构， 包括氮化硅膜和多晶硅膜的层结构; 多晶硅膜在预平面化时用作蚀刻阻挡层; 并且在通过CMP方法研磨时，氮化硅膜用作蚀刻阻挡层，以便同时去除过量绝缘膜和多晶硅膜以暴露作为活性区域的基板的表面，由此 可获得具有令人满意的形状的沟槽隔离。

公开(公告)号：US06218262B1

公开(公告)日：2001-04-17

申请号：US09200469

申请日：1998-11-27

申请人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

发明人： Takashi Kuroi ,  Maiko Sakai ,  Katsuyuki Horita ,  Hirokazu Sayama

IPC分类号： H01L21335

CPC分类号： H01L23/544 ,  H01L21/0274 ,  H01L21/32139 ,  H01L21/76229 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

摘要翻译： 本发明提供一种半导体器件，其包括沟槽型元件隔离，其在不劣化器件能力的情况下进行精确对准，以及制造这种半导体器件的方法。 由于在沟槽（10A）的边缘邻近区域中形成虚拟栅电极（14A），所以实现了不产生蚀刻余量的结构。 此外，由于在虚拟栅极电极（14A）的表面上设置高差，使得高度差反映了氧化硅膜（2A）的表面和硅表面之间的预备高度差 基板（1），可以使用伪栅电极本身（14A）作为对准标记。

公开(公告)号：US6127737A

公开(公告)日：2000-10-03

申请号：US943520

申请日：1997-10-03

申请人： Takashi Kuroi ,  Katsuyuki Horita ,  Maiko Sakai ,  Yasuo Inoue

发明人： Takashi Kuroi ,  Katsuyuki Horita ,  Maiko Sakai ,  Yasuo Inoue

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/544

CPC分类号： H01L21/76232 ,  H01L21/76229

摘要： In a semiconductor device with a trench-type element isolation structure, alignment can be performed with high accuracy without any deterioration in device performance. The surfaces of silicon oxide films (2B, 2C) embedded in trenches (10B, 10C) of an element forming region including a memory cell region (11B) and a peripheral circuit region (11C) in a semiconductor substrate (1), respectively, are almost level with the surface of the semiconductor substrate (1). On the other hand, the surface of a silicon oxide film (2A) embedded in a trench (10A) is formed lower than the surface of the semiconductor substrate (1).

摘要翻译： 在具有沟槽型元件隔离结构的半导体器件中，可以高精度地进行对准，而不会使器件性能下降。 分别在半导体衬底（1）中嵌入包括存储单元区域（11B）的元件形成区域和外围电路区域（11C）的沟槽（10B，10C）中的氧化硅膜（2B，2C）的表面， 几乎与半导体衬底（1）的表面一致。 另一方面，嵌入在沟槽（10A）中的氧化硅膜（2A）的表面形成为低于半导体衬底（1）的表面。

公开(公告)号：US6034409A

公开(公告)日：2000-03-07

申请号：US24312

申请日：1998-02-17

申请人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

发明人： Maiko Sakai ,  Takashi Kuroi ,  Katsuyuki Horita

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/10

CPC分类号： H01L21/76232

摘要： A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1

摘要翻译： 一种半导体器件，包括半导体衬底，形成在衬底中并具有包括侧壁和底表面的内壁的沟槽，沉积在内壁上的氧化硅膜和沉积在氧化硅膜上的掩埋氧化膜以埋入 沟槽，其中侧壁具有从基板的表面到沟槽的底表面以第一轮廓角A1倾斜的侧壁的第二轮廓角A2和第三轮廓角A3，并且轮廓角具有 A1