LAMINATED AND SINTERED CERAMIC CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE INCLUDING THE CIRCUIT BOARD
    2.
    发明申请
    LAMINATED AND SINTERED CERAMIC CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE INCLUDING THE CIRCUIT BOARD 有权
    层压和烧结陶瓷电路板,以及包括电路板的半导体封装

    公开(公告)号:US20130049202A1

    公开(公告)日:2013-02-28

    申请号:US13331253

    申请日:2011-12-20

    IPC分类号: H01L23/48 H05K1/09 H05K1/00

    摘要: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit hoard with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

    摘要翻译: 在根据本发明的层压和烧结陶瓷电路板中,面内导体的至少一部分被精细地排列,使得细衬面内导体的横截面的形状是梯形,并且高度 (a)中,梯形截面的下基部的长度(c)和上基部的长度(d)以及梯形截面的梯形截面的下基座之间的间隔(b) 在与板的主表面平行的平面中相邻的面内导体满足一定关系。 这提供了在小型和短路(薄)半导体封装中具有低开路故障率,短路故障率和高温和高湿度的高可靠性的层压陶瓷电路板。