公开(公告)号：US20240365467A1

公开(公告)日：2024-10-31

申请号：US18407677

申请日：2024-01-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hong MIN ,  Jong Eun PARK

IPC: H05K1/03 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/115 ,  H05K3/46 ,  H05K2201/096 ,  H05K2201/09827

Abstract: The present disclosure relates to a printed circuit board include: a core layer including an inorganic insulating layer, a resin layer covering at least a portion of an external side surface of the inorganic insulating layer, and a second insulating layer covering at least a portion of a lower surface of each of the inorganic insulating layer and the resin layer and having an interlayer boundary with the resin layer; a first wiring layer disposed on an upper surface of the core layer; and a second wiring layer disposed on a lower surface of the core layer. The external side surface of the inorganic insulating layer is substantially perpendicular to at least one of the upper surface and the lower surface of the inorganic insulating, and a manufacturing method therefor.

公开(公告)号：US20240357736A1

公开(公告)日：2024-10-24

申请号：US18684457

申请日：2022-08-15

Applicant: HITACHI ASTEMO, LTD.

Inventor： Takanori SEKIGUCHI ,  Takayuki DEGUCHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0268 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/09827 ,  H05K2203/045 ,  H05K2203/1121

Abstract: An electronic component is mounted on a surface layer of a multilayer substrate constituting a wiring substrate, and a signal wire of the surface layer is electrically connected to the electronic component. A conductor pad for contact with an inspection probe is composed of a via and a solder filled in an internal opening portion thereof. The via has a laser-processed taper-shaped hole with a metal-plated inner peripheral surface and connects the inter-layer connection between the signal wire of the surface layer and a signal wire of the inner layer. The solder is filled in the opening portion of the via by filling, heating and melting solder material therein. Since the peripheral edge portion is solidified first at the time of the cooling and the solidification, the middle part is recessed compared to the peripheral edge portion. This ensures a reliable contact of the inspection probe.

公开(公告)号：US20240341033A1

公开(公告)日：2024-10-10

申请号：US18625662

申请日：2024-04-03

Applicant: IBIDEN CO., LTD.

Inventor： Masashi KUWABARA ,  Susumu KAGOHASHI

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/115 ,  H05K3/4038 ,  H05K2201/0245 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2203/06

Abstract: A wiring substrate includes a first build-up part including first insulating and conductor layers, and via conductors, and a second build-up part including second insulating and conductor layers. The first build-up part is laminated on the second build-up part. The minimum wiring width of wirings in the first conductor layers is smaller than the minimum wiring width of wirings in the second conductor layers. The minimum inter-wiring distance of the wirings in the first conductor layers is smaller than the minimum inter-wiring distance of the wirings in the second conductor layers. The first conductor layers and via conductors include a first layer and a second layer. The first layer of each via conductor is covering inner wall surface in a via opening and has a first portion and a second portion. The first portion has a portion formed closer to the center of the via opening than the second portion.

公开(公告)号：US20240334601A1

公开(公告)日：2024-10-03

申请号：US18242843

申请日：2023-09-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sangho Jeong ,  Jongeun Park ,  Yongduk Lee ,  Kihwan Kim ,  Changhwa Park

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/09827

Abstract: A circuit board includes a first insulation layer, a circuit wire positioned on the first insulation layer, a second insulation layer covering the circuit wire and overlapping a portion of the circuit wire, and having a via hole including a first side wall and a second side wall having different tilt angles and extending in the thickness direction of the first insulation layer, a first seed layer covering the first side wall and the second side wall of the via hole, a second seed layer positioned in the via hole and covering the first seed layer, a third seed layer positioned on an upper surface of the second insulation layer and including the same material as the second seed layer, a first conductive layer positioned on the second seed layer, and a second conductive layer positioned on the third seed layer.

公开(公告)号：US12101878B2

公开(公告)日：2024-09-24

申请号：US17906214

申请日：2021-03-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Dong Hwa Lee ,  Yong Suk Kim

IPC: H05K1/03 ,  H05K1/02 ,  H05K1/05 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/0366 ,  H05K1/0373 ,  H05K1/056 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0275 ,  H05K2201/068 ,  H05K2201/096 ,  H05K2201/09827

Abstract: A circuit board according to an embodiments includes an insulating portion comprising a plurality of insulating layers, wherein the insulating portion includes: a first insulating portion; a second insulating portion disposed on the first insulating portion and having a coefficient of thermal expansion corresponding to the first insulating portion; and a third insulating portion disposed under the first insulating portion and having a coefficient of thermal expansion corresponding to the first insulating portion; wherein the first insulating portion includes a prepreg including glass fibers, and wherein the second and third insulating portions include a resin coated copper (RCC) with a coefficient of thermal expansion in the range of 10 to 65 (10−6 m/m·k).

公开(公告)号：US11972993B2

公开(公告)日：2024-04-30

申请号：US17320646

申请日：2021-05-14

Applicant: CORNING INCORPORATED

Inventor： Rachel Eileen Dahlberg ,  Tian Huang ,  Yuhui Jin ,  Garrett Andrew Piech ,  Daniel Ohen Ricketts

IPC: H01L23/15 ,  B23K26/00 ,  B23K26/06 ,  B23K26/062 ,  B23K26/402 ,  B23K26/53 ,  B23K26/55 ,  C03C15/00 ,  C03C23/00 ,  H01L21/48 ,  H01L23/498 ,  B23K26/0622 ,  B23K26/064 ,  B23K26/073 ,  B23K26/36 ,  B23K103/00 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L23/15 ,  B23K26/0006 ,  B23K26/06 ,  B23K26/062 ,  B23K26/402 ,  B23K26/53 ,  B23K26/55 ,  C03C15/00 ,  C03C23/0025 ,  B23K26/0617 ,  B23K26/0622 ,  B23K26/0624 ,  B23K26/0626 ,  B23K26/064 ,  B23K26/0738 ,  B23K26/36 ,  B23K2103/54 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T428/24273

Abstract: Silica-containing substrates including vias with a narrow waist, electronic devices incorporating a silica-containing substrate, and methods of forming vias with narrow waist in silica-containing substrates are disclosed. In one embodiment, an article includes a silica-containing substrate including greater than or equal to 85 mol % silica, a first surface, a second surface opposite the first surface, and a via extending through the silica-containing substrate from the first surface toward the second surface. The via includes a first diameter at the first surface wherein the first diameter is less than or equal to 100 μm, a second diameter at the second surface wherein the first diameter is less than or equal to 100 μm, and a via waist between the first surface and the second surface. The via waist has a waist diameter that is less than the first diameter and the second diameter such that a ratio between the waist diameter and each of the first diameter and the second diameter is less than or equal to 75%.

公开(公告)号：US11924980B2

公开(公告)日：2024-03-05

申请号：US17575717

申请日：2022-01-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yusuke Kamitsubo ,  Tomohiro Furumura

IPC: H05K1/02 ,  H05K1/03 ,  H05K3/46

CPC classification number: H05K3/4635 ,  H05K1/0277 ,  H05K1/036 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/09827

Abstract: A method for manufacturing a multilayer substrate including first and second insulating resin base material layers including different materials, includes configuring a conductor film-attached insulating resin base material with a conductor film on the first insulating resin base material layer, or a second conductor film-attached insulating resin base material with a conductor film on a main surface of the first insulating resin base material layer including a main surface of a stacked body including at least the first insulating resin base material layer, and stacking the first or second conductor film-attached insulating resin base material and another base material layer such that the conductor film is in contact with the second insulating resin base material layer. An adhesion strength of the first insulating resin base material layer to the conductor film is higher than an adhesion strength of the second insulating resin base material layer to the conductor film.

公开(公告)号：US11903129B2

公开(公告)日：2024-02-13

申请号：US17691772

申请日：2022-03-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Chi Seong Kim ,  Won Seok Lee ,  Guh Hwan Lim ,  Jin Uk Lee ,  Jin Oh Park

IPC: H05K1/02 ,  H01L23/13 ,  H01L23/66 ,  H05B45/20 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/119 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0044 ,  H05K2201/09827 ,  H05K2201/09854

Abstract: A printed circuit board includes: a first insulating material; and a second insulating material disposed on one surface of the first insulating material, and including first and second cavities having depths different from each other. At least one groove portion is disposed in a side surface of each of the first and second cavities.

公开(公告)号：US11882656B2

公开(公告)日：2024-01-23

申请号：US17708486

申请日：2022-03-30

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Daisuke Minoura

IPC: H05K1/11 ,  H05K3/38 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/113 ,  H05K3/383 ,  H05K3/389 ,  H05K3/0035 ,  H05K3/428 ,  H05K2201/096 ,  H05K2201/09454 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.

公开(公告)号：US20230395766A1

公开(公告)日：2023-12-07

申请号：US18032212

申请日：2021-10-14

Applicant: TDK CORPORATION

Inventor： Tomohisa MITOSE ,  Kenichi KAWABATA ,  Susumu TANIGUCHI ,  Akiko SEKI

IPC: H01L33/62 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L33/62 ,  H01L24/16 ,  H01L24/13 ,  H05K1/181 ,  H01L24/73 ,  H01L24/32 ,  H01L2933/0066 ,  H01L2224/73204 ,  H01L2224/32237 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/81815 ,  H01L2224/81192 ,  H05K2201/10106 ,  H05K2201/09472 ,  H01L2924/12041 ,  H05K2201/09827

Abstract: A mounting board includes an electronic component having at least a pair of first terminals, and a circuit board having at least a pair of second terminals. The first terminal and the second terminal are bonded to each other by a bonding material. The first terminal, the second terminal, and the bonding material are disposed inside a recessed portion formed in a resin layer such that the periphery thereof is surrounded by the resin layer. When a total thickness of the first terminal, the second terminal, and the bonding material is a dimension h1, the dimension h1 is 1 μm to 20 μm. When a width of the first terminal is a dimension d1 and a width of the recessed portion of the resin layer is a dimension d2, a value of (dimension d2—dimension d1) is 10 μm or smaller.