公开(公告)号：US08779846B2

公开(公告)日：2014-07-15

申请号：US13549748

申请日：2012-07-16

申请人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Heather Lynn Hanson ,  Wei Huang ,  Charles Robert Lefurgy ,  Karthick Rajamani

发明人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Heather Lynn Hanson ,  Wei Huang ,  Charles Robert Lefurgy ,  Karthick Rajamani

IPC分类号： G06F1/10 ,  G06F3/02 ,  H03K17/16 ,  H03K19/003

CPC分类号： G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for improving the performance of a digital circuit is provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

摘要翻译： 在说明性实施例中提供了一种用于改善数字电路的性能的方法。 使用数字电路中的控制环来调整数字电路的实际工作频率，响应于数字电路的工作状态的变化来调整实际频率。 从向数字电路提供电力的电压调节器接收由数字电路汲取的电流的测量值。 接收过电流目标电流值。 调整从电压调节器到数字电路的输出电压，使得由数字电路汲取的电流不超过过电流目标电流值。

公开(公告)号：US20130035797A1

公开(公告)日：2013-02-07

申请号：US13549748

申请日：2012-07-16

申请人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Heather Lynn Hanson ,  Wei Huang ,  Charles Robert Lefurgy ,  Karthick Rajamani

发明人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Heather Lynn Hanson ,  Wei Huang ,  Charles Robert Lefurgy ,  Karthick Rajamani

IPC分类号： G05D11/00

CPC分类号： G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for improving the performance of a digital circuit is provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

摘要翻译： 在说明性实施例中提供了一种用于改善数字电路的性能的方法。 使用数字电路中的控制环来调整数字电路的实际工作频率，响应于数字电路的工作状态的变化来调整实际频率。 从向数字电路提供电力的电压调节器接收由数字电路汲取的电流的测量值。 接收过电流目标电流值。 调整从电压调节器到数字电路的输出电压，使得由数字电路汲取的电流不超过过电流目标电流值。

公开(公告)号：US20130033306A1

公开(公告)日：2013-02-07

申请号：US13195684

申请日：2011-08-01

申请人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Heather Lynn Hanson ,  Wei Huang ,  Charles Robert Lefurgy ,  Karthick Rajamani

发明人： Malcolm Scott Allen-Ware ,  John Bruce Carter ,  Heather Lynn Hanson ,  Wei Huang ,  Charles Robert Lefurgy ,  Karthick Rajamani

IPC分类号： G05F1/10

CPC分类号： G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method, system, and computer program product for improving the performance of a digital circuit are provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

摘要翻译： 在说明性实施例中提供了用于改善数字电路的性能的方法，系统和计算机程序产品。 使用数字电路中的控制环来调整数字电路的实际工作频率，响应于数字电路的工作状态的变化来调整实际频率。 从向数字电路提供电力的电压调节器接收由数字电路汲取的电流的测量值。 接收过电流目标电流值。 调整从电压调节器到数字电路的输出电压，使得由数字电路汲取的电流不超过过电流目标电流值。

公开(公告)号：US08719527B2

公开(公告)日：2014-05-06

申请号：US13460044

申请日：2012-04-30

申请人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Kshitij Sudan ,  Joanne B. Rawson

发明人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Freeman Leigh Rawson, III ,  Kshitij Sudan

IPC分类号： G06F12/06

CPC分类号： G06F12/08 ,  G06F1/3275 ,  G06F9/5094 ,  G06F2212/1028 ,  G11C5/04 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.

摘要翻译： 在说明性实施例中提供了用于增加存储器的容量的方法。 使用使用处理器执行的应用程序，其中所述存储器包括一组等级，所述存储器被配置为形成冷层和热层，所述冷层包括来自所述存储器中的所述一组等级的第一子群， 热层包括来自内存中的一组排名的第二个子集。 确定存储器访问请求所指向的页面是否位于存储器中的冷层中。 响应于页面位于存储器的冷层中，通过以延迟处理存储器访问请求来限制存储器访问请求的处理。

公开(公告)号：US08738875B2

公开(公告)日：2014-05-27

申请号：US13295196

申请日：2011-11-14

申请人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Kshitij Sudan ,  Joanne R. Rawson

发明人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Freeman Leigh Rawson, III ,  Kshitij Sudan

IPC分类号： G06F12/06

CPC分类号： G06F12/08 ,  G06F1/3275 ,  G06F9/5094 ,  G06F2212/1028 ,  G11C5/04 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.

摘要翻译： 在说明性实施例中提供了用于增加存储器容量的系统和计算机程序产品。 使用使用处理器执行的应用程序，其中所述存储器包括一组等级，所述存储器被配置为形成冷层和热层，所述冷层包括来自所述存储器中的所述一组等级的第一子群， 热层包括来自内存中的一组排名的第二个子集。 确定存储器访问请求所指向的页面是否位于存储器中的冷层中。 响应于页面位于存储器的冷层中，通过以延迟处理存储器访问请求来限制存储器访问请求的处理。

公开(公告)号：US20130124814A1

公开(公告)日：2013-05-16

申请号：US13295196

申请日：2011-11-14

申请人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Kshitij Sudan ,  Joanne R Rawson

发明人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Freeman Leigh Rawson, III ,  Kshitij Sudan

IPC分类号： G06F12/00

CPC分类号： G06F12/08 ,  G06F1/3275 ,  G06F9/5094 ,  G06F2212/1028 ,  G11C5/04 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.

摘要翻译： 在说明性实施例中提供了用于增加存储器容量的系统和计算机程序产品。 使用使用处理器执行的应用程序，其中所述存储器包括一组等级，所述存储器被配置为形成冷层和热层，所述冷层包括来自所述存储器中的所述等级的队列的第一子集， 热层包括来自内存中的一组排名的第二个子集。 确定存储器访问请求所指向的页面是否位于存储器中的冷层中。 响应于页面位于存储器的冷层中，通过以延迟处理存储器访问请求来限制存储器访问请求的处理。

公开(公告)号：US20130124810A1

公开(公告)日：2013-05-16

申请号：US13460044

申请日：2012-04-30

申请人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Kshitij Sudan ,  Joanne B. Rawson

发明人： John Bruce Carter ,  Wei Huang ,  Karthick Rajamani ,  Freeman Leigh Rawson, III ,  Kshitij Sudan

IPC分类号： G06F12/02

CPC分类号： G06F12/08 ,  G06F1/3275 ,  G06F9/5094 ,  G06F2212/1028 ,  G11C5/04 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.

摘要翻译： 在说明性实施例中提供了用于增加存储器的容量的方法。 使用使用处理器执行的应用程序，其中所述存储器包括一组等级，所述存储器被配置为形成冷层和热层，所述冷层包括来自所述存储器中的所述等级的队列的第一子集， 热层包括来自内存中的一组排名的第二个子集。 确定存储器访问请求所指向的页面是否位于存储器中的冷层中。 响应于页面位于存储器的冷层中，通过以延迟处理存储器访问请求来限制存储器访问请求的处理。

公开(公告)号：US09009503B2

公开(公告)日：2015-04-14

申请号：US13542532

申请日：2012-07-05

申请人： Malcolm Scott Allen-Ware ,  Wael El-Essawy ,  Alexandre Peixoto Ferreira ,  Thomas Walter Keller, Jr. ,  Karthick Rajamani ,  Juan Carlos Rubio

发明人： Malcolm Scott Allen-Ware ,  Wael El-Essawy ,  Alexandre Peixoto Ferreira ,  Thomas Walter Keller, Jr. ,  Karthick Rajamani ,  Juan Carlos Rubio

IPC分类号： G06F1/26 ,  H02J13/00

CPC分类号： H02J13/002 ,  H04B3/54 ,  H04L12/6418

摘要： A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit.

摘要翻译： 在说明性实施例中提供了用于将数据处理系统与功率分支电路相关联的方法，系统和计算机程序产品。 一组信号中的每个信号与功率信号组合以形成一组组合信号，功率信号包括数据处理系统的第一功率使用和调制信号的第二功率使用。 在一个周期中确定组合信号组中每个组合信号中对应信号的幅度。 使用鉴别逻辑，确定调制信号是否存在于功率信号中。 响应于产生肯定结果的识别逻辑，数据处理系统与功率分支电路相关。

公开(公告)号：US20140013126A1

公开(公告)日：2014-01-09

申请号：US13542532

申请日：2012-07-05

申请人： Malcolm Scott Allen-Ware ,  Wael El-Essawy ,  Alexandre Peixoto Ferreira ,  Thomas Walter Keller, JR. ,  Karthick Rajamani ,  Juan Carlos Rubio

发明人： Malcolm Scott Allen-Ware ,  Wael El-Essawy ,  Alexandre Peixoto Ferreira ,  Thomas Walter Keller, JR. ,  Karthick Rajamani ,  Juan Carlos Rubio

IPC分类号： G06F1/26

CPC分类号： H02J13/002 ,  H04B3/54 ,  H04L12/6418

摘要： A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit.

摘要翻译： 在说明性实施例中提供了用于将数据处理系统与功率分支电路相关联的方法，系统和计算机程序产品。 一组信号中的每个信号与功率信号组合以形成一组组合信号，功率信号包括数据处理系统的第一功率使用和调制信号的第二功率使用。 在一个周期中确定组合信号组中每个组合信号中对应信号的幅度。 使用鉴别逻辑，确定调制信号是否存在于功率信号中。 响应于产生肯定结果的识别逻辑，数据处理系统与功率分支电路相关。

公开(公告)号：US09026818B2

公开(公告)日：2015-05-05

申请号：US13593672

申请日：2012-08-24

申请人： Heather L. Hanson ,  Charles Robert Lefurgy ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

发明人： Heather L. Hanson ,  Charles Robert Lefurgy ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

IPC分类号： G06F1/00 ,  G06F9/50

CPC分类号： G06F9/5061 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

摘要： A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

摘要翻译： 为基于优先级的功率上限提供了一种机制。 电力管理控制器识别数据处理系统的一组分区的一组优先级。 功率管理控制器确定数据处理系统的测量功率是否超过数据处理系统的功率限制。 响应于超过功率上限的测量功率，功率管理控制器向一组组件致动器发送一组命令，以使用该组来调整与该组分组相关联的一组组件的一组操作参数中的一个或多个 的优先事项。 该组件致动器调整与该组件相关联的一组操作参数中的一个或多个，以便降低数据处理系统的功率消耗。