Polyisocyanate mixtures, processes for preparing the same and uses therefor
    4.
    发明授权
    Polyisocyanate mixtures, processes for preparing the same and uses therefor 有权
    多异氰酸酯混合物,其制备方法和用途

    公开(公告)号:US07985479B2

    公开(公告)日:2011-07-26

    申请号:US12143283

    申请日:2008-06-20

    IPC分类号: B32B27/40 C08G18/76 B35C5/00

    摘要: Polyisocyanate mixtures, their preparation by reacting aromatic polyisocyanate mixtures and nitrogen-containing polyetherol mixtures, and their use as an isocyanate component for the preparation of moisture-curing adhesives, said polyisocyanate mixtures comprising: (A) 15 to 35 wt. % of diphenylmethane diisocyanate with 2 aromatic rings; (3) 10 to 30 wt. % of polymeric diphenylmethane diisocyanate with 3 or more aromatic rings; and (C) 40 to 75 wt. % of an isocyanate-functional polyurethane; wherein the polyisocyanate mixture has an isocyanate content of 12 to 20 wt. %, an isocyanate functionality of >2.4, a viscosity of

    摘要翻译: 多异氰酸酯混合物,它们通过使芳族多异氰酸酯混合物和含氮聚醚醚混合物反应制备,以及它们作为用于制备湿固化粘合剂的异氰酸酯组分的用途,所述多异氰酸酯混合物包含:(A)15至35重量% %二苯基甲烷二异氰酸酯与2个芳环; (3)10〜30重量% %的具有3个或更多芳环的聚合二苯基甲烷二异氰酸酯; 和(C)40〜75重量% %的异氰酸酯官能聚氨酯; 其中所述多异氰酸酯混合物的异氰酸酯含量为12〜20wt。 %,异氰酸酯官能度> 2.4,在25℃粘度<10,000mPa·s,剪切速率80l / s。

    POLYISOCYANATE MIXTURES, PROCESSES FOR PREPARING THE SAME AND USES THEREFOR
    5.
    发明申请
    POLYISOCYANATE MIXTURES, PROCESSES FOR PREPARING THE SAME AND USES THEREFOR 有权
    聚异氰酸酯混合物,其制备方法及其用途

    公开(公告)号:US20080318060A1

    公开(公告)日:2008-12-25

    申请号:US12143283

    申请日:2008-06-20

    IPC分类号: B32B27/40 C08G18/76

    摘要: Polyisocyanate mixtures, their preparation by reacting aromatic polyisocyanate mixtures and nitrogen-containing polyetherol mixtures, and their use as an isocyanate component for the preparation of moisture-curing adhesives, said polyisocyanate mixtures comprising: (A) 15 to 35 wt. % of diphenylmethane diisocyanate with 2 aromatic rings; (3) 10 to 30 wt. % of polymeric diphenylmethane diisocyanate with 3 or more aromatic rings; and (C) 40 to 75 wt. % of an isocyanate-functional polyurethane; wherein the polyisocyanate mixture has an isocyanate content of 12 to 20 wt. %, an isocyanate functionality of >2.4, a viscosity of

    摘要翻译: 多异氰酸酯混合物,它们通过使芳族多异氰酸酯混合物和含氮聚醚醚混合物反应制备,以及它们作为用于制备湿固化粘合剂的异氰酸酯组分的用途,所述多异氰酸酯混合物包含:(A)15至35重量% %二苯基甲烷二异氰酸酯与2个芳环; (3)10〜30重量% %的具有3个或更多芳环的聚合二苯基甲烷二异氰酸酯; 和(C)40〜75重量% %的异氰酸酯官能聚氨酯; 其中所述多异氰酸酯混合物的异氰酸酯含量为12〜20wt。 %,异氰酸酯官能度> 2.4,在25℃下粘度<10,000mPa.s,剪切速率80l / s。

    HOLDING DEVICE FOR A STRINGED INSTRUMENT
    8.
    发明申请
    HOLDING DEVICE FOR A STRINGED INSTRUMENT 失效
    持有仪器的仪器

    公开(公告)号:US20090151538A1

    公开(公告)日:2009-06-18

    申请号:US12030428

    申请日:2008-02-13

    IPC分类号: G10G5/00

    CPC分类号: G10G5/00

    摘要: Holding device and method for holding an instrument. The holding device includes a housing, at least one holding arm having a mounting section coupled to a holding section through at least one offset lever section, and a resetting device structured and arranged to act eccentrically on the mounting section. The at least one holding arm is rotatable about a longitudinal axis of the mounting section.

    摘要翻译: 握持装置的保持装置和方法。 保持装置包括壳体,至少一个保持臂,其具有通过至少一个偏移杆部分联接到保持部分的安装部分,以及构造和布置成偏心地安装在安装部分上的复位装置。 所述至少一个保持臂可围绕安装部分的纵向轴线旋转。

    Multi-stage numeric counter oscillator
    9.
    发明授权
    Multi-stage numeric counter oscillator 有权
    多级数字计数振荡器

    公开(公告)号:US07064616B2

    公开(公告)日:2006-06-20

    申请号:US10748488

    申请日:2003-12-29

    申请人: Peter Reichert

    发明人: Peter Reichert

    IPC分类号: H03L7/00

    CPC分类号: G06F1/0328

    摘要: A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.

    摘要翻译: 公开了一种数字计数器振荡器,其包括商累加器和余数累加器。 商累加器具有用于接收QUOTIENT值的可编程输入,参考时钟输入和多位输出。 该输出适于发送表示累积商数的输出值OUT。 响应于每个参考时钟周期,多位输出增加预定量。 剩余累加器包括可编程输入,用于接收相应的REMAINDER和DIVISOR值,参考时钟输入和表示累积的数字余数和小于预定数字整数的多位输出。 剩余累加器还包括具有用于接收编程除数值的第一输入的比较器和用于接收余数累加器多位输出的第二输入。 当余数多位输出达到预定义的整数值时,比较器可操作以产生用于应用于商积累器的递增进位信号。

    Pattern generator for a packet-based memory tester
    10.
    发明授权
    Pattern generator for a packet-based memory tester 有权
    用于基于分组的内存测试器的模式生成器

    公开(公告)号:US06389525B1

    公开(公告)日:2002-05-14

    申请号:US09227690

    申请日:1999-01-08

    IPC分类号: G06F1200

    摘要: A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.

    摘要翻译: 公开了一种用于存储器测试器中的模式发生器,用于将分组地址和数据信号提供给基于分组的未被测试的存储器。 图案生成器包括用于生成外部分组存储器地址信号的地址源。 外部分组存储器地址信号表示被测存储器中的多个可寻址存储器元件。 多个数据发生器并行布置并耦合到地址源的输出端以接收分组存储器地址信号的至少一部分。 每个数据发生器具有逻辑可操作以从分组地址导出内部地址。 内部地址对应于被测存储器内的单独存储元件。 定序器设置在数据发生器的输出处,以便将数据发生器输出以分组波形分布以供应用于待测存储器。