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公开(公告)号：US5311509A
公开(公告)日：1994-05-10
申请号：US832127
申请日：1992-02-06
申请人： Marco Heddes , Ronald Luijten
发明人： Marco Heddes , Ronald Luijten
CPC分类号： H04L49/3081 , H04L49/20 , H04L49/3063 , H04L2012/5653 , H04L49/30 , H04L49/55
摘要： The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.
摘要翻译： 本发明涉及一种数据传输系统，涉及将用户帧转换为固定长度小区的方法，例如， ATM（异步传输模式），使得固定长度的小区可以通过小区处理交换结构（11）传输。 该方法的硬件实现包括两个部分：发射机（12.1）和接收机（13.1），它们都是包括交换结构（11）的交换子系统（10）的一部分。 发射机（12.1）缓冲用户数据并将它们分段成固定长度的小区，以便通过所述交换机（11）传输。 接收器部分（13.1）在接收到这些单元时重新组合用户数据。
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公开(公告)号：US5271000A
公开(公告)日：1993-12-14
申请号：US804133
申请日：1991-12-06
CPC分类号： H04L43/50 , H04L12/2697 , H04Q11/0478 , H04L2012/5628
摘要： The dynamic functional behavior of geographically distributed fast packet switching systems, including those which accommodate high-priority circuit switched traffic and low-priority packet switched traffic, are tested in real-time by sending test packets from one or more source nodes through the system to specific destinations that comprise a test packet analyzer. The test packets have the same structure as the data packets, but in their payload portion carry the entire information required to perform the testing. The nature of that test information depends on the characteristics of a set of predefined system errors the verification system is supposed to identify. For detecting errors, the test information would include an input address indicating the source of the test packet, a sequence number defining the order in which the packet should arrive at the destination, time bits relating to the packet length and/or to the expected packet transmission delay, and a cyclic redundancy code which covers the entire contents of the test packet, including its control portion. Each analyzer at a receiving station operates autonomously from the senders and processes all received traffic in real-time; this enables it to recognize all defined system errors, even those occurring with very low probability, at the packet level.
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3.发明授权High speed buffer management of share memory using linked lists and plural buffer managers for processing multiple requests concurrently 失效使用链表对共享存储器进行高速缓冲管理，并且多个缓冲管理器同时处理多个请求
公开(公告)号：US5432908A
公开(公告)日：1995-07-11
申请号：US313656
申请日：1994-09-27
申请人： Marco Heddes , Ronald Luijten
发明人： Marco Heddes , Ronald Luijten
CPC分类号： G06F5/06 , G06F2205/064
摘要： The present invention relates to the management of a large and fast memory. The memory is logically subdivided into several smaller parts called buffers. A buffer-control memory (11) having as many sections for buffer-control records as buffers exist is employed together with a buffer manager (12). The buffer manager (12) organizes and controls the buffers by keeping the corresponding buffer-control records in linked lists. A request manager (20), as pad of the buffer manager (12), does or does not grant the allocation of a buffer. A stack manager (21) controls the free buffers by keeping the buffer-control records in a stack (23.1), and a FIFO manager (22) keeps the buffer-control records of allocated buffers in FIFO linked lists (23.2-23.n). The stack and FIFO managers (20), (21) are parts of the buffer manager (12), too.
摘要翻译： 本发明涉及大型和快速存储器的管理。 存储器在逻辑上细分为几个称为缓冲器的较小部件。 缓冲器管理器（12）与缓冲器控制存储器（11）一起使用，缓冲器控制存储器（11）具有与存储缓冲器控制记录一样多的部分。 缓冲管理器（12）通过将相应的缓冲器控制记录保持在链表中来组织和控制缓冲器。 作为缓冲器管理器（12）的焊盘的请求管理器（20）执行或不准许缓冲器的分配。 堆栈管理器（21）通过将缓冲器控制记录保持在堆栈（23.1）中来控制空闲缓冲器，并且FIFO管理器（22）将分配的缓冲器的缓冲器控制记录保持在FIFO链接列表中（23.2-23.n ）。 栈和FIFO管理器（20），（21）也是缓冲管理器（12）的一部分。
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4.发明授权Network processor with single interface supporting tree search engine and CAM 失效具有单界面支持树搜索引擎和CAM的网络处理器公开(公告)号：US07953077B2
公开(公告)日：2011-05-31
申请号：US11457952
申请日：2006-07-17
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , G11C15/00 , H04L45/745 , H04L45/7453 , H04L49/90
摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.
摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。
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5.发明申请System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory 审中-公开具有由具有分布式片上共享存储器和外部共享存储器的片上网络链接的可编程处理元件阵列的片上系统公开(公告)号：US20100191911A1
公开(公告)日：2010-07-29
申请号：US12639325
申请日：2009-12-16
CPC分类号： G06F15/16
摘要： An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.
摘要翻译： 具有可编程处理元件阵列的集成电路和由片上通信网络链接的存储器接口。 每个处理元件包括多个处理核心和本地存储器。 存储器接口块可操作地耦合到外部存储器和片上通信网络。 存储器接口支持通过片上通信网络响应于从阵列的处理元件传送的消息来访问外部存储器。 阵列的多个处理元件的一部分本地存储器的一部分以及外部存储器的一部分都被分配以在执行分配在其上的编程操作期间存储由阵列的多个处理元件共享的数据。
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6.发明申请SYSTEM FOR MANAGING MULTI-FIELD CLASSIFICATION RULES RELATING TO INGRESS CONTEXTS AND EGRESS CONTEXTS 失效用于管理与生态系统和排气系统有关的多领域分类规则的系统公开(公告)号：US20080249973A1
公开(公告)日：2008-10-09
申请号：US12143641
申请日：2008-06-20
IPC分类号： G06N5/02
CPC分类号： G06N99/005
摘要： The present invention relates to a system for managing a plurality of multi-field classification rules. The system provides a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The system also includes a network processor for classifying packets of information, wherein the network processor is programmed to utilize the first table and the second table to identify any rules relating to the ingress context and any one rules relating to the egress context that match a search key.
摘要翻译： 本发明涉及一种用于管理多个多场分类规则的系统。 该系统提供第一表，其包括对应于与入口上下文相关的多个规则的多个条目，以及第二表，其包括对应于与出口上下文相关的多个规则的多个条目。 该系统还包括用于对信息包进行分类的网络处理器，其中网络处理器被编程为利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索匹配的出口上下文相关的任何规则 键。
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7.发明授权公开(公告)号：US07412431B2
公开(公告)日：2008-08-12
申请号：US10832958
申请日：2004-04-27
CPC分类号： G06N99/005
摘要： The present invention relates to a method for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.
摘要翻译： 本发明涉及一种用于管理多个多场分类规则的方法。 该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。 该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。
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公开(公告)号：US20080162525A1
公开(公告)日：2008-07-03
申请号：US12048667
申请日：2008-03-14
IPC分类号： G06F17/30
CPC分类号： H03M7/30 , Y10S707/99942
摘要： Method for compressing search tree structures used in rule classification is provided. The method includes classifying packets based on filter rules, compressing a tree structure comprising multiple levels of single bit test nodes and leaf nodes, storing the compressed tree structure in a first memory structure of a storage such that the multiple levels of single bit test nodes and leaf nodes can be accessed from the first memory structure through a single memory access of the storage, collecting single bit test nodes of the tree structure that are in a lowest level of the tree structure, storing only the collected single bit test nodes within a second memory structure of the storage that is contiguous to the first memory structure, collecting leaf nodes of the tree structure, and storing only the collected leaf nodes within a third memory structure of the storage that is contiguous to second memory structure.
摘要翻译： 提供了规则分类中使用的搜索树结构的压缩方法。 该方法包括基于过滤器规则对分组进行分类，压缩包括多个单位测试节点和叶节点的树结构，将压缩的树结构存储在存储器的第一存储器结构中，使得多个单位测试节点和 可以通过存储器的单个存储器访问从第一存储器结构访问叶节点，收集处于树结构的最低级别的树结构的单位测试节点，仅在第二存储器结构中存储所收集的单个位测试节点 与第一存储器结构相邻的存储器的存储器结构，收集树结构的叶节点，以及仅存储所收集的叶节点在与第二存储器结构相邻的存储器的第三存储器结构内。
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公开(公告)号：US07149749B2
公开(公告)日：2006-12-12
申请号：US10453245
申请日：2003-06-03
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
IPC分类号： G06F17/30
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： A technique is provided to either insert or delete a leaf in a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as either a leaf to be inserted or deleted. Using the pattern, the tree is walked once to identify the location of the leaf to be deleted or the location where the leaf is to be inserted. If it is a delete operation, the leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. If it is an insert operation, the tree is walked a second time to insert the leaf and reform or create any PSCB in the chain that needs to be reformed or created. The technique also is applicable to inserting or deleting a prefix of a prefix.
摘要翻译： 提供了一种技术来插入或删除具有直接表的Patricia树中的叶子，以及多个PSCB，其解码树中的叶子的图案的部分，而不关闭树的功能。 具有图案的叶被识别为要插入或删除的叶。 使用图案，树一次走一次，以确定要删除的叶的位置或叶被插入的位置。 如果是删除操作，则要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。 如果是插入操作，则树第二次移动以插入叶，并在需要重新创建或创建的链中重新构建或创建任何PSCB。 该技术也适用于插入或删除前缀的前缀。
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公开(公告)号：US06963868B2
公开(公告)日：2005-11-08
申请号：US10448528
申请日：2003-05-30
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall
CPC分类号： H04L45/00 , H04L45/56 , H04L45/7457 , Y10S707/99933
摘要： A tree structure and method to organize routing information for processing messages within a network, each message being associated with a search key of “n” bits. The processing determines where to send the message next. The structure has a direct table (DT) of 2x entries for decoding the first “x” bits of the search key, and one or more pattern search control blocks (PSCB's), each having 2m entries for decoding subsequent groups of “m” bits. Each PSCB entry and DT entry includes a pointer to data associated with a specific route, if at this point a specific routing table entry is a potential match to the search key or a pointer to a subsequent PSCB if the end of a search trail is not identified. Each PSCB entry DT entry also indicates that the search has been resolved to the end of the search trail.
摘要翻译： 一种用于组织用于处理网络内的消息的路由信息的树结构和方法，每个消息与“n”比特的搜索关键字相关联。 该处理确定接下来发送消息的位置。 该结构具有用于对搜索关键字的第一个“x”比特进行解码的2个“<”条目的直接表（DT），以及一个或多个模式搜索控制块（PSCB），每个具有2个
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