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    Distribution of communications between paths
    4.
    发明授权
    Distribution of communications between paths 失效
    路径之间的通信分配

    公开(公告)号：US07406091B2

    公开(公告)日：2008-07-29

    申请号：US10756668

    申请日：2004-01-12

    申请人： Michael A. Schroeder ,  Craig W. Warner ,  Gary Belgrave Gostin ,  Mark Edward Shaw

    发明人： Michael A. Schroeder ,  Craig W. Warner ,  Gary Belgrave Gostin ,  Mark Edward Shaw

    IPC分类号： H04L12/28 ,  H03M13/00 ,  G06F15/173

    CPC分类号： H04L45/00 ,  H04L45/24

    摘要： Distributing communications between paths, comprises providing a plurality of destinations, providing a plurality of communications paths such that each of the plurality of destinations can be accessed over each of the plurality of communications paths, defining destination addresses interleaved over the plurality of destinations, sending communications from a source to a plurality of the interleaved addresses, and selecting different ones of the plurality of paths for successive communications that are sent to addresses on different destinations, wherein the path for a communication is selected using at least a part of the address of the communication.

    摘要翻译： 分布路径之间的通信包括提供多个目的地，提供多个通信路径，使得可以通过多个通信路径中的每一个访问多个目的地中的每一个，定义在多个目的地上交织的目的地地址，发送通信 从源到多个交错地址，以及选择多个路径中的不同路径用于连续通信，所述连续通信被发送到不同目的地上的地址，其中，使用至少一部分地址选择通信的路径 通讯。

    Processor interrupt filtering
    6.
    发明授权
    Processor interrupt filtering 失效
    处理器中断过滤

    公开(公告)号：US07099977B2

    公开(公告)日：2006-08-29

    申请号：US10756434

    申请日：2004-01-12

    申请人： Huai-Ter Victor Chong ,  Gary Belgrave Gostin ,  Craig W. Warner

    发明人： Huai-Ter Victor Chong ,  Gary Belgrave Gostin ,  Craig W. Warner

    IPC分类号： G06F13/00

    CPC分类号： G06F9/4812

    摘要： A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dropped. If the interrupt source is in a local partition, the interrupt is delivered. If the interrupt source is in the interrupt set and not in the local partition, the interrupt is processed in accordance with at least one of a target enable register and a vector enable register.

    摘要翻译： 一种在具有布置在至少两个分区中的多个处理器的系统中处理中断消息的方法。 中断消息被解码以识别中断源。 如果中断源不在中断集中，则中断被中断。 如果中断源在本地分区中，则中断被传递。 如果中断源处于中断集合而不在本地分区中，则根据目标使能寄存器和向量使能寄存器中的至少一个来处理中断。

    Communication in partitioned computer systems
    7.
    发明授权
    Communication in partitioned computer systems 失效
    分区计算机系统中的通信

    公开(公告)号：US07277994B2

    公开(公告)日：2007-10-02

    申请号：US10947673

    申请日：2004-09-23

    申请人： Gary Belgrave Gostin ,  Nathan Dirk Zelle

    发明人： Gary Belgrave Gostin ,  Nathan Dirk Zelle

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/0692 ,  G06F12/0284

    摘要： One embodiment of a computer system has processors, having address spaces the processors can address directly. Each address space is directly linked to at least one other address space by memory within more than its own address space. The total size of the address spaces within the system linked together either directly or through directly linked address spaces is greater than the address space any resource within the system can address directly.

    摘要翻译： 计算机系统的一个实施例具有处理器，其具有处理器可直接寻址的地址空间。 每个地址空间由多于其自己的地址空间内的存储器直接链接到至少一个其他地址空间。 系统中直接或通过直接链接的地址空间链接在一起的系统中的地址空间的总大小大于系统中任何资源可以直接解决的地址空间。

    Memory controller connection to RAM using buffer interface
    8.
    发明授权
    Memory controller connection to RAM using buffer interface 有权
    内存控制器使用缓冲区连接到RAM

    公开(公告)号：US08612684B2

    公开(公告)日：2013-12-17

    申请号：US11999834

    申请日：2007-12-07

    申请人： Theodore Carter Briggs ,  John Michael Wastlick ,  Gary Belgrave Gostin

    发明人： Theodore Carter Briggs ,  John Michael Wastlick ,  Gary Belgrave Gostin

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/1673 ,  G06F12/0817

    摘要： Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.

    摘要翻译： 提供了用于控制存储器控制器和连接到存储器的至少两个逻辑存储器总线之间的数据传输的存储器控​​制装置和方法，包括存储器控制器; 一个缓冲区 连接控制器和缓冲器的双向数据总线; 连接控制器和缓冲器的控制接口，缓冲器连接至至少两个用于存储器读和写操作的逻辑存储器总线，该缓冲器包括用于在控制器和逻辑存储器总线之间缓冲数据的数据存储区域，以及逻辑电路 从控制器解码存储器接口控制命令; 以及连接缓冲器和每个逻辑存储器总线的数据访问和控制总线，以控制存储器读和写操作。

    Successful transactions
    9.
    发明授权
    Successful transactions 有权
    成功交易

    公开(公告)号：US07606253B2

    公开(公告)日：2009-10-20

    申请号：US10756667

    申请日：2004-01-12

    申请人： Gregg Bernard Lesartre ,  Gary Belgrave Gostin

    发明人： Gregg Bernard Lesartre ,  Gary Belgrave Gostin

    IPC分类号： H04L12/54

    CPC分类号： H04L1/1874 ,  H04L1/0061

    摘要： A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

    摘要翻译： 采用串行化器和解串器的数据通信架构可以减少数据通信延迟。 在说明性实现中，数据通信架构通过通信链路传送数据。 该架构维护各种机制，以提升数据通信速度，避免通信链路停机。 这些机制执行的功能包括但不限于处理不确定的数据到达时间，检测单位和多位错误，处理通信链路故障，解决故障链路训练，识别和标记数据已损坏，以及识别和处理成功的数据事务 通信链接。

    Memory controller connection to RAM using buffer interface
    10.
    发明授权
    Memory controller connection to RAM using buffer interface 有权
    内存控制器使用缓冲区连接到RAM

    公开(公告)号：US07363427B2

    公开(公告)日：2008-04-22

    申请号：US10756446

    申请日：2004-01-12

    申请人： Theodore Carter Briggs ,  John Michael Wastlick ,  Gary Belgrave Gostin

    发明人： Theodore Carter Briggs ,  John Michael Wastlick ,  Gary Belgrave Gostin

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1673 ,  G06F12/0817

    摘要： A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.

    摘要翻译： 用于计算机的存储器子系统控制器和缓冲器以及用于存储器标签操作的第二缓冲器。 缓冲器通过两个双向数据总线连接到存储器控制器。 控制器通过缓冲器将存储器地址传递到存储器子系统数据总线来操作存储器子系统。 控制器和缓冲区之间的单向控制接口向缓冲器提供存储器控制命令，并向存储器缓冲区提供存储器标签信息。 控制器对存储器执行读取和写入操作，通常用多个写入操作来交织多个读取操作。 读取和写入数据被临时存储在缓冲设备上，而其他操作正在被执行以优化计算机的存储器子系统的数据带宽。