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1.发明授权
公开(公告)号：US5970354A
公开(公告)日：1999-10-19
申请号：US987117
申请日：1997-12-08
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28123
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. An oxide layer is formed over the implanted portion of the polysilicon layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译： 提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。 栅极的长度可以通过使用间隔物来调节。 该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。 优选地，在掩模层中形成开口，该开口限定栅极导体的位置。 开口的宽度可以通过使用间隔物变窄。 由开口限定的多晶硅层的一部分注入n型杂质。 在多晶硅层的注入部分上形成氧化物层。 蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。 随后在栅极导体附近形成LDD区域和源极/漏极区域。
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2.发明授权Stacked mask integration technique for advanced CMOS transistor formation 失效叠层掩模集成技术，用于先进的CMOS晶体管形成
公开(公告)号：US5946579A
公开(公告)日：1999-08-31
申请号：US987277
申请日：1997-12-09
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28052 , H01L21/28123 , H01L21/32137
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. A silicide layer is formed upon the upper surface of the exposed polysilicon layer. An oxide layer is formed over the silicide layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译： 提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。 栅极的长度可以通过使用间隔物来调节。 该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。 优选地，在掩模层中形成开口，该开口限定栅极导体的位置。 开口的宽度可以通过使用间隔物变窄。 由开口限定的多晶硅层的一部分注入n型杂质。 在暴露的多晶硅层的上表面上形成硅化物层。 在硅化物层上形成氧化物层。 蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。 随后在栅极导体附近形成LDD区域和源极/漏极区域。
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3.发明授权Method and structure for isolating semiconductor devices after transistor formation 失效在晶体管形成之后隔离半导体器件的方法和结构公开(公告)号：US06184566B2
公开(公告)日：2001-02-06
申请号：US09150776
申请日：1998-09-10
IPC分类号： H01L2176
CPC分类号： H01L21/823418 , H01L21/76237 , H01L21/823425 , H01L21/823481 , Y10S257/90
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.
摘要翻译： 一种用于隔离半导体器件的方法，包括提供半导体衬底。 半导体衬底包括横向移位的源极/漏极区域和沟道区域。 第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。 第一和第二晶体管具有公共源极/漏极区域。 通过公共源极/漏极区形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被分成电隔离的第一和第二源极/漏极区域，由此第一晶体管与 第二晶体管。
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公开(公告)号：US6117760A
公开(公告)日：2000-09-12
申请号：US968682
申请日：1997-11-12
IPC分类号： H01L21/768 , H01L23/528 , H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each interconnect is advantageously dictated by the thickness of the spacer layer rather than by the minimum feature size of a lithographically patterned masking layer. In an embodiment, a first and second conductive interconnects are formed a spaced distance apart upon a semiconductor topography. The first and second interconnects are defined using optical lithography and an etch technique. A dielectric layer is CVD deposited across the exposed surfaces of the first and second interconnects and of the semiconductor topography. The CVD deposition conditions are controlled so as to form a relatively thin spacers laterally adjacent the sidewalls of the interconnects. A conductive material is then deposited across into a trench arranged between the first and second interconnects, and CMP polished such that the upper surface of the conductive material is at an elevational level proximate that of the surfaces of the interconnects. A third interconnect is thereby formed within the trench laterally adjacent the first and second interconnects.
摘要翻译： 提供了一种技术，用于通过沉积的介电隔离层在半导体形貌上形成横向间隔开的互连。 每个互连之间的横向距离有利地由隔离层的厚度而不是光刻图案化掩模层的最小特征尺寸决定。 在一个实施例中，第一和第二导电互连在半导体形貌上分开形成间隔距离。 第一和第二互连使用光刻和蚀刻技术来定义。 介电层是跨越第一和第二互连的暴露表面和半导体形貌的CVD沉积的。 控制CVD沉积条件以形成横向邻近互连侧壁的较薄的间隔件。 然后将导电材料沉积到布置在第一和第二互连之间的沟槽中，并且CMP抛光，使得导电材料的上表面处于靠近互连表面的上表面。 因此，在沟槽内形成第三互连件，横向地邻近第一和第二互连。
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5.发明授权Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance 失效具有多个LDD和/或源极/漏极注入步骤以增强电路性能的集成电路
公开(公告)号：US6107129A
公开(公告)日：2000-08-22
申请号：US38511
申请日：1998-03-11
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/7835
摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
摘要翻译： 形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。 晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。 多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。 因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。
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6.发明授权CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein 失效CMOS集成电路通过使用可移除间隔物在不对称PMOS结之间产生不对称的NMOS结形成，用于优化植入其中的掺杂剂的热扩散率
公开(公告)号：US5837572A
公开(公告)日：1998-11-17
申请号：US781461
申请日：1997-01-10
IPC分类号： H01L21/8238 , H01L21/82
CPC分类号： H01L21/823814 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.
摘要翻译： 提供具有NMOS晶体管和PMOS晶体管的集成电路。 NMOS晶体管结区优选地在具有预定义的退火温度的PMOS晶体管结区之后形成在选择的注入步骤之后。 NMOS和PMOS晶体管结都被分级，使得漏极区域包括相对较大的LDD注入区域，并且源极结不包括。 无论在植入较高浓度源/漏或MDD植入物的源中预先存在LDD区域。 因此，随后的集成电路是具有不对称晶体管结和仔细控制的注入和退火序列的CMOS电路。 通过控制退火温度使得n型植入物的扩散距离相对于p型植入物保持或至少优化不对称结。 通过调节比以前的n型植入物少的p型植入物的植入后退火温度来控制扩散性。
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7.发明授权Selectively doped channel region for increased I.sub.Dsat and method for making same 失效选择性掺杂通道区域用于增加IDat及其制备方法
公开(公告)号：US5804497A
公开(公告)日：1998-09-08
申请号：US695101
申请日：1996-08-07
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L21/70
CPC分类号： H01L29/66537 , H01L21/823807 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A selectively doped MOS transistor channel includes a deep impurity distribution and shallow impurity distribution. The deep impurity distribution is formed within high energy implant with an impurity of conductivity type opposite to the conductivity type of the source/drain regions of the transistor. In the n-channel regions, the deep impurity distribution preferably includes boron ions. The deep impurity distribution acts as a channel stop such that adjacent source/drain regions of the like type transistors are not inadvertently coupled during circuit operation. The shallow impurity distribution acts as a threshold implant by precisely controlling the doping of the transistor channel in the vicinity of the silicon oxide interface. The peak concentration of the shallow impurity distribution is located at a depth below the silicon surface which is greater than a depth typically associated with a threshold adjust implant. Because the impurity concentration of the shallow impurity distribution drops off rapidly from the peak concentration value, the concentration at the upper surface of the silicon substrate is not significantly greater than the doping of the silicon substrate itself. The light doping in the channel region of the transistor results in a substantially reduced threshold voltage for the transistor. Preferably, the threshold voltage of both the n-channel and p-channel devices has an absolute value of approximately 250 Mv. The lower threshold voltage translates into a higher I.sub.Dsat when the transistor is operated under normal conditions (e.g., V.sub.Gs =3 volts, V.sub.Ds =3 volts, and V.sub.sb =0 volts.)
摘要翻译： 选择掺杂的MOS晶体管沟道包括深杂质分布和浅杂质分布。 深度杂质分布形成在高能量注入内，其杂质的导电类型与晶体管的源/漏区的导电类型相反。 在n沟道区域中，深杂质分布优选包括硼离子。 深杂质分布充当通道阻挡，使得类似晶体管的相邻源极/漏极区在电路操作期间不会无意中耦合。 通过精确地控制在氧化硅界面附近的晶体管沟道的掺杂，浅杂质分布充当阈值注入。 浅杂质分布的峰值浓度位于硅表面下方的深度，该深度大于通常与阈值调整植入物相关联的深度。 由于浅杂质分布的杂质浓度从峰值浓度值迅速下降，所以硅衬底上表面的浓度不会明显大于硅衬底本身的掺杂。 在晶体管的沟道区域中的轻掺杂导致晶体管的阈值电压显着降低。 优选地，n沟道和p沟道器件的阈值电压具有约250Mv的绝对值。 当晶体管在正常条件下操作时（例如，VGs = 3V，VDs = 3V，Vsb = 0V），较低的阈值电压转换为更高的IDat。
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8.发明授权Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias 失效响应于电信号的测试结构，用于确定导体相对于通孔的光刻不对准
公开(公告)号：US6118137A
公开(公告)日：2000-09-12
申请号：US925383
申请日：1997-09-08
IPC分类号： H01L23/528 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L23/528 , H01L2924/0002
摘要： The present invention advantageously provides a method for determining lithographic misalignment of a conductive element relative to a via. An electrically measured test structure is provided which is designed to have targeted via areas shifted from midlines of corresponding targeted conductor areas. Further, the test structure is designed to have a test pad that electrically communicates with the targeted via areas. Design specifications of the test structure require the midlines of the conductor areas to be offset from the via areas by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to each of the conductors while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a conductor is misaligned from its desired location. Using the electrical responses for all the conductors, it is possible to determine the direction and amount of misalignment.
摘要翻译： 本发明有利地提供了一种用于确定导电元件相对于通孔的光刻未对准的方法。 提供了一种电测试的测试结构，其被设计成具有从相应的目标导体区域的中线偏移的目标通孔区域。 此外，测试结构被设计成具有与目标通孔区域电连通的测试垫。 测试结构的设计规范要求导体区域的中线通过不同的距离偏离通孔区域。 上述方法涉及处理设计的测试结构。 然后可以将电信号施加到每个导体，同时它也被施加到测试垫。 所产生的电响应应与导体与其所需位置不对准的距离成正比。 使用所有导体的电响应，可以确定未对准的方向和量。
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9.发明授权Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor 失效在形成栅极导体之前，使用在源极和漏极区域之间形成硅化物的晶体管制造
公开(公告)号：US5918130A
公开(公告)日：1999-06-29
申请号：US929197
申请日：1997-09-08
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66621 , H01L29/7834 , Y10S148/10 , Y10S438/951
摘要： The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them. Spacers may be formed on opposed sidewall surfaces of the sacrificial material within the opening. A gate oxide is then formed across the exposed region, followed by the formation of a polysilicon gate conductor across the gate oxide. A polycide is formed across the gate conductor before the sacrificial material is removed.
摘要翻译： 本发明有利地提供了一种形成晶体管的方法，其中在晶体管的制造期间，其中形成硅化物接触区域到结。 可以使用单个高温退火来形成硅化物接触区域，因为防止在栅极氧化物的侧壁附近形成硅化物。 在一个实施例中，首先将掺杂剂转移到硅基衬底的横向区域中以形成植入区域。 然后使用高温退火在所述注入区域上形成硅化物层。 在硅化物层和衬底之间沉积牺牲材料。 通过牺牲材料和硅化物层垂直地形成连续的开口，暴露基板的一部分。 然后将与先前注入的掺杂剂相反的类型的掺杂剂注入暴露的衬底区域中以形成沟道。 因此，注入区被分离成具有介于它们之间的通道的源区和漏区。 间隔件可以形成在开口内的牺牲材料的相对的侧壁表面上。 然后在暴露区域之间形成栅极氧化物，随后在栅极氧化物上形成多晶硅栅极导体。 在除去牺牲材料之前，跨越栅极导体形成多晶硅化物。
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10.发明授权
公开(公告)号：US5916715A
公开(公告)日：1999-06-29
申请号：US925382
申请日：1997-09-08
CPC分类号： G03F7/70633 , G01R31/2805 , G03F7/70658 , G01R31/2813
摘要： The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.
摘要翻译： 本发明有利地提供了一种用于确定通孔相对于电活动区域的光刻未对准的方法。 提供电测量的测试结构，其被设计成具有从目标有源区域的中线偏移的目标通孔区域。 此外，测试结构被设计成具有与目标有源区域电连通的测试焊盘。 测试结构的设计规范要求目标通孔区域通过变化的距离偏离有效区域的中线。 上述方法涉及处理设计的测试结构。 然后可以将电信号施加到耦合到每个通孔的导体，同时它也被施加到测试垫。 所产生的电响应应与通孔与其所需位置不对准的距离成正比。 使用所有通孔的电响应，可以确定未对准的方向和量。
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