公开(公告)号：US06252276B1

公开(公告)日：2001-06-26

申请号：US09377183

申请日：1999-08-19

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L2978

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L29/518 ,  H01L29/66825

摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

摘要翻译： 提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。 有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。 这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

公开(公告)号：US5972751A

公开(公告)日：1999-10-26

申请号：US143090

申请日：1998-08-28

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L29/518 ,  H01L29/66825

摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

摘要翻译： 提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。 有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。 这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

公开(公告)号：US06989319B1

公开(公告)日：2006-01-24

申请号：US10718707

申请日：2003-11-24

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21/265

CPC分类号： H01L21/265 ,  H01L21/28176 ,  H01L21/28273

摘要： Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.

摘要翻译： 提供了用于显着减少具有多晶硅特征和上覆电介质层的半导体器件中的电子俘获的方法和装置。 所述方法和装置在靠近覆盖的介电层的界面附近使用多晶硅特征内的富氮区域。 所述方法包括通过至少部分上覆介质层选择性地注入氮离子并进入多晶硅特征以在多晶硅特征内形成初始氮浓度分布。 接下来，将多晶硅特征中的温度升高到足够高的温度，例如使用快速热退火（RTA）技术，其使得初始氮浓度分布由于大部分氮朝着界面迁移而改变 与上层电介质层或与下层的界面。 因此，多晶硅特征具有在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域。 氮的迁移进一步形成位于第一富氮区和第二富氮区之间的连续的还原氮区。 连续的还原氮区域具有比第一富氮区域和第二富氮区域低的氮浓度。 已发现第一富氮区域减少多晶硅特征内的电子俘获。 因此，例如，在其中多晶硅特征是浮动栅极的非易失性存储器件中，可以通过减少浮置栅极中的俘获电子的数量来显着地避免存储器件的伪编程。

公开(公告)号：US6001713A

公开(公告)日：1999-12-14

申请号：US154074

申请日：1998-09-16

申请人： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

发明人： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

IPC分类号： H01L21/28 ,  H01L21/265

CPC分类号： H01L21/28273

摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.

摘要翻译： 提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。 该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。 所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。 这在浮动栅极内形成初始氮浓度分布。 然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。 浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。 因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。 已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。 与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。 因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

公开(公告)号：US5856946A

公开(公告)日：1999-01-05

申请号：US831571

申请日：1997-04-09

申请人： Vei-Han Chan ,  Sameer Haddad ,  Chi Chang

发明人： Vei-Han Chan ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/12

摘要： A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.

摘要翻译： 在存储器单元编程期间具有受控栅极电流注入的存储器，其中编程电路在编程周期期间将时变电压施加到存储器单元的控制栅极。 在编程周期期间，随时间变化的电压产生从通道区域到浮动栅极的电子流量的基本恒定的速率。

公开(公告)号：US06410956B1

公开(公告)日：2002-06-25

申请号：US09478864

申请日：2000-01-07

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L2976

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US5999452A

公开(公告)日：1999-12-07

申请号：US63688

申请日：1998-04-21

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US5912489A

公开(公告)日：1999-06-15

申请号：US940674

申请日：1997-09-30

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US06266275B1

公开(公告)日：2001-07-24

申请号：US09410512

申请日：1999-09-30

申请人： Paul-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Paul-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C700

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。