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    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
    1.
    发明申请
    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme 有权
    非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）具有减少功率的列复用方案

    公开(公告)号：US20050091477A1

    公开(公告)日：2005-04-28

    申请号：US10996140

    申请日：2004-11-23

    申请人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G06F15/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme
    2.
    发明申请
    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme 有权
    具有减少功率的多路复用方案的非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）

    公开(公告)号：US20080089144A1

    公开(公告)日：2008-04-17

    申请号：US11777054

    申请日：2007-07-12

    申请人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme
    3.
    发明申请
    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme 有权
    具有减少功率的多路复用方案的非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）

    公开(公告)号：US20100177581A1

    公开(公告)日：2010-07-15

    申请号：US12617570

    申请日：2009-11-12

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06 ,  G11C8/16 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
    5.
    发明授权
    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme 有权
    非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）具有减少功率的列复用方案

    公开(公告)号：US07251175B2

    公开(公告)日：2007-07-31

    申请号：US10996140

    申请日：2004-11-23

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method of making the multi-port register file memory. The storage elements are arranged in N rows and M columns and store data, each column having at least one output channel or circuit. Two read port pairs are coupled to each of the storage elements and a plurality of differential sensing devices or circuits. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and at least one of the sensing device. The method of forming the multi-port register file memory comprises determining the number of storage elements and arranging the storage elements in the N rows and M columns, each column having an output channel. The number of read ports is determined based, at least in part, on the number of storage elements. The number of differential sensing devices is determined based, at least in part, on a number of the output channels. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和同步或异步操作的其他电路，以及一种制造多端口寄存器文件存储器的方法。 存储元件被布置成N行和M列并存储数据，每列具有至少一个输出通道或电路。 两个读端口对耦合到每个存储元件和多个差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置中的至少一个。 形成多端口寄存器文件存储器的方法包括确定存储元件的数量并将存储元件排列在N行和M列中，每列具有输出通道。 至少部分地基于存储元件的数量确定读取端口的数量。 至少部分地基于输出通道的数量确定差分感测装置的数量。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
    6.
    发明授权
    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme 有权
    非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）具有减少功率的列复用方案

    公开(公告)号：US07986570B2

    公开(公告)日：2011-07-26

    申请号：US12617570

    申请日：2009-11-12

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Low leakage data retention flip flop
    9.
    发明授权
    Low leakage data retention flip flop 有权
    低泄漏数据保持触发器

    公开(公告)号：US08076965B2

    公开(公告)日：2011-12-13

    申请号：US12082597

    申请日：2008-04-10

    申请人： Gregory Djaja ,  Mark Slamowitz ,  Karthik Chandrasekharan

    发明人： Gregory Djaja ,  Mark Slamowitz ,  Karthik Chandrasekharan

    IPC分类号： H03K3/289

    CPC分类号： H03K3/0372 ,  H03K3/012

    摘要： A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.

    摘要翻译： 所公开的实施例是一种低泄漏数据保持触发器，其包括用于在睡眠模式期间保留数据的主电路，其中主电路被配置为在睡眠模式期间接收降低的电源电压。 触发器包括具有低阈值电压晶体管的从电路，其中从电路在睡眠模式期间被关断。 在各种实施例中，主电路可以利用高阈值电压，标准阈值电压或低阈值电压晶体管。 类似地，从电路可以利用高阈值电压，标准阈值电压或低阈值电压晶体管。 要开始睡眠模式，主电路接收降低的电源电压，并且从电路耦合到地，因此被关断。 在睡眠模式期间，从电路实际上没有泄漏电流，并且主电路经历了减小的漏电流。