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    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
    1.
    发明申请
    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme 有权
    非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）具有减少功率的列复用方案

    公开(公告)号：US20050091477A1

    公开(公告)日：2005-04-28

    申请号：US10996140

    申请日：2004-11-23

    申请人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G06F15/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme
    2.
    发明申请
    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme 有权
    具有减少功率的多路复用方案的非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）

    公开(公告)号：US20080089144A1

    公开(公告)日：2008-04-17

    申请号：US11777054

    申请日：2007-07-12

    申请人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme
    3.
    发明申请
    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme 有权
    具有减少功率的多路复用方案的非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）

    公开(公告)号：US20100177581A1

    公开(公告)日：2010-07-15

    申请号：US12617570

    申请日：2009-11-12

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06 ,  G11C8/16 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
    5.
    发明授权
    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme 有权
    非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）具有减少功率的列复用方案

    公开(公告)号：US07251175B2

    公开(公告)日：2007-07-31

    申请号：US10996140

    申请日：2004-11-23

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method of making the multi-port register file memory. The storage elements are arranged in N rows and M columns and store data, each column having at least one output channel or circuit. Two read port pairs are coupled to each of the storage elements and a plurality of differential sensing devices or circuits. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and at least one of the sensing device. The method of forming the multi-port register file memory comprises determining the number of storage elements and arranging the storage elements in the N rows and M columns, each column having an output channel. The number of read ports is determined based, at least in part, on the number of storage elements. The number of differential sensing devices is determined based, at least in part, on a number of the output channels. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和同步或异步操作的其他电路，以及一种制造多端口寄存器文件存储器的方法。 存储元件被布置成N行和M列并存储数据，每列具有至少一个输出通道或电路。 两个读端口对耦合到每个存储元件和多个差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置中的至少一个。 形成多端口寄存器文件存储器的方法包括确定存储元件的数量并将存储元件排列在N行和M列中，每列具有输出通道。 至少部分地基于存储元件的数量确定读取端口的数量。 至少部分地基于输出通道的数量确定差分感测装置的数量。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
    6.
    发明授权
    Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme 有权
    非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）具有减少功率的列复用方案

    公开(公告)号：US07986570B2

    公开(公告)日：2011-07-26

    申请号：US12617570

    申请日：2009-11-12

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    System and method using a one-time programmable memory cell
    9.
    发明申请
    System and method using a one-time programmable memory cell 有权
    使用一次性可编程存储单元的系统和方法

    公开(公告)号：US20060044861A1

    公开(公告)日：2006-03-02

    申请号：US10929609

    申请日：2004-08-31

    申请人： Douglas Smith ,  Myron Buer ,  Bassem Radieddine

    发明人： Douglas Smith ,  Myron Buer ,  Bassem Radieddine

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16

    摘要： A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element comprises a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.

    摘要翻译： 一次性可编程设备包括控制器，保护系统，静态存储元件和锁存器，其可被称为基于锁存器的一次可编程（OTP）元件。 在一个示例中，静态存储元件包括用作电阻元件的薄栅极氧化物，其根据其是否被熔断将锁存器设置为两种状态之一。

    Anti-fuse device
    10.
    发明申请
    Anti-fuse device 有权
    防熔断器

    公开(公告)号：US20050258482A1

    公开(公告)日：2005-11-24

    申请号：US11094269

    申请日：2005-03-31

    申请人： Akira Ito ,  Douglas Smith ,  Myron Buer

    发明人： Akira Ito ,  Douglas Smith ,  Myron Buer

    IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/112 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

    摘要翻译： 反熔丝器件包括衬底和形成在衬底中的侧向间隔开的源极和漏极区域。 在源区和漏区之间形成通道。 在通道上形成栅极和栅极氧化物，并且在沟道中形成轻掺杂的源极和漏极延伸区域。 轻掺杂的源极和漏极区域分别从源极和漏极区域延伸穿过沟道，占据通道的主要部分。 通过向栅极和源极区域和漏极区域中的至少一个施加电力来执行反熔丝的编程，以分解栅极氧化物，从而最小化栅极和沟道之间的电阻。