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12 条记录 (耗时 0.024 秒)

    Method for fabricating an insulation collar in a trench capacitor
    1.
    发明授权
    Method for fabricating an insulation collar in a trench capacitor 失效
    在沟槽电容器中制造绝缘套环的方法

    公开(公告)号：US06777303B2

    公开(公告)日：2004-08-17

    申请号：US10153045

    申请日：2002-05-22

    申请人： Martin Schrems ,  Anke Krasemann ,  Moritz Haupt ,  Sabine Steck ,  Daniel Köhler

    发明人： Martin Schrems ,  Anke Krasemann ,  Moritz Haupt ,  Sabine Steck ,  Daniel Köhler

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L29/66181

    摘要： A trench capacitor is formed with an insulation collar. After the formation of the trench, firstly an insulating layer is deposited, from which layer the insulation collar will be subsequently formed. Afterward, the trench is partly filled with a sacrificial filling material and a thin patterning layer is deposited thereon. Spacers are formed from that layer and cover the insulating layer in the upper region of the trench. Afterward, the sacrificial filling material and the insulating layer are completely removed in the lower region of the trench. As a result, the insulation collar is produced in the upper region of the trench.

    摘要翻译： 沟槽电容器形成有绝缘套环。 在形成沟槽之后，首先沉积绝缘层，从该层将形成绝缘套环。 之后，沟槽部分地填充有牺牲填充材料，并且在其上沉积薄图案层。 间隔由该层形成并覆盖沟槽上部区域中的绝缘层。 之后，牺牲填充材料和绝缘层在沟槽的下部区域被完全去除。 结果，在沟槽的上部区域中产生绝缘套环。

    Fabrication method for a semiconductor structure
    5.
    发明申请
    Fabrication method for a semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US20050245042A1

    公开(公告)日：2005-11-03

    申请号：US11099962

    申请日：2005-04-06

    申请人： Moritz Haupt ,  Andreas Klipp ,  Hans-Peter Sperlich ,  Momtchil Stavrev ,  Stephan Wege

    发明人： Moritz Haupt ,  Andreas Klipp ,  Hans-Peter Sperlich ,  Momtchil Stavrev ,  Stephan Wege

    IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242

    CPC分类号： H01L21/76232

    摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

    摘要翻译： 本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。 在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 执行V等离子体蚀刻步骤，用于在沟槽（5）中形成线层（10）的V轮廓; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

    Capacitor with hemispherical silicon-germanium grains and a method for making the same
    8.
    发明申请
    Capacitor with hemispherical silicon-germanium grains and a method for making the same 审中-公开
    具有半球形硅锗晶粒的电容器及其制造方法

    公开(公告)号：US20080067568A1

    公开(公告)日：2008-03-20

    申请号：US11521607

    申请日：2006-09-15

    申请人： Saad Abbasi ,  Moritz Haupt

    发明人： Saad Abbasi ,  Moritz Haupt

    IPC分类号： H01L29/94 ,  H01L21/20

    CPC分类号： H01L29/945 ,  H01L27/1087 ,  H01L28/84 ,  H01L29/66181

    摘要： A method of forming hemispherical silicon-germanium grains within a capacitor which includes providing the semiconductor substrate and forming the capacitor surface in the substrate is provided. The method also includes forming a layer of grained silicon-germanium on the surface of the capacitor. Another aspect of the present invention is seen in a capacitor formed in the substrate of a semiconductor device. A trench is formed in the substrate having a surface and a first capacitor electrode is formed in the semiconductor substrate around the trench. A layer of grained silicon-germanium is formed on the surface of the trench. A dielectric layer is formed on the grained silicon-germanium layer and a second capacitor electrode is formed on the dielectric layer.

    摘要翻译： 提供了一种在电容器内形成半球形硅 - 锗晶粒的方法，该方法包括提供半导体衬底并在衬底中形成电容器表面。 该方法还包括在电容器的表面上形成粒状硅 - 锗层。 在形成在半导体器件的衬底中的电容器中可以看到本发明的另一方面。 在具有表面的基板中形成沟槽，并且在沟槽周围的半导体衬底中形成第一电容器电极。 在沟槽的表面上形成一层粒状硅 - 锗。 在晶粒硅锗层上形成电介质层，在电介质层上形成第二电容电极。

    Fabrication method for a semiconductor structure
    9.
    发明授权
    Fabrication method for a semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US07265023B2

    公开(公告)日：2007-09-04

    申请号：US11099962

    申请日：2005-04-06

    申请人： Moritz Haupt ,  Andreas Klipp ,  Hans-Peter Sperlich ,  Momtchill Stavrev ,  Stephan Wege

    发明人： Moritz Haupt ,  Andreas Klipp ,  Hans-Peter Sperlich ,  Momtchill Stavrev ,  Stephan Wege

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76232

    摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

    摘要翻译： 本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。 在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 进行用于在沟槽（5）中形成线层（10）的V轮廓的V等离子体蚀刻步骤; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。