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    Soft FEC with parity check
    1.
    发明授权
    Soft FEC with parity check 有权

    公开(公告)号：US12101186B2

    公开(公告)日：2024-09-24

    申请号：US18210823

    申请日：2023-06-16

    Applicant: Marvell Asia Pte Ltd

    Inventor： Jamal Riani ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

    IPC: H04L1/00 ,  H04L25/06

    CPC classification number: H04L1/0071 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0045 ,  H04L1/0046 ,  H04L1/0055 ,  H04L1/0063 ,  H04L25/067

    Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

    Optimizing host / module interface
    2.
    发明授权
    Optimizing host / module interface 有权

    公开(公告)号：US12009951B2

    公开(公告)日：2024-06-11

    申请号：US17186897

    申请日：2021-02-26

    Applicant: Marvell Asia Pte Ltd.

    Inventor： Todd Rope ,  Ilya Lyubomirsky ,  Whay Sing Lee ,  Arash Farhoodfar

    IPC: H04L25/03 ,  G06N20/00 ,  H04B10/079

    CPC classification number: H04L25/03261 ,  G06N20/00 ,  H04B10/0795

    Abstract: Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.

    Line side multiplexers with protection switching
    3.
    发明授权
    Line side multiplexers with protection switching 有权

    公开(公告)号：US11470038B1

    公开(公告)日：2022-10-11

    申请号：US16878412

    申请日：2020-05-19

    Applicant: Marvell Asia Pte, Ltd.

    Inventor： Whay Sing Lee ,  Arash Farhoodfar

    IPC: H04L61/10 ,  H04L1/00 ,  H04L101/622

    Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

    Network systems and methods for CXL standard
    4.
    发明授权
    Network systems and methods for CXL standard 有权

    公开(公告)号：US11388268B1

    公开(公告)日：2022-07-12

    申请号：US16777655

    申请日：2020-01-30

    Applicant: Marvell Asia Pte, Ltd.

    Inventor： Kumaran David Siva ,  Arash Farhoodfar ,  Radhakrishnan L. Nagarajan

    IPC: G06F13/12 ,  G06F13/38 ,  H04B10/278 ,  H04B10/80 ,  H04L1/00 ,  H04L69/10 ,  H04L69/12 ,  H04L69/16 ,  H04L69/18

    Abstract: A first processing unit for a computer server apparatus includes a first circuit configured to process a first type of data to be transmitted and received over a communication channel in accordance with a peripheral component interconnect express (PCIe) protocol, a second circuit configured to process a second type of data to be transmitted and received over the communication channel in accordance with a compute express link (CXL) protocol, and an optical communication interface configured to modulate the first type of data and the second type of data into a first signal in a PAM format to be transmitted over the communication channel to a second processing unit and receive, from the second processing unit over the communication channel, a second signal including either one of the first type of data and the second type of data modulated in the PAM format.

    NETWORK TRANSCEIVER WITH CLOCK SHARING BETWEEN DIES
    8.
    发明公开
    NETWORK TRANSCEIVER WITH CLOCK SHARING BETWEEN DIES 审中-公开

    公开(公告)号：US20230185757A1

    公开(公告)日：2023-06-15

    申请号：US18063479

    申请日：2022-12-08

    Applicant: Marvell Asia Pte Ltd

    Inventor： Michael Lewis Takefman ,  Arash Farhoodfar ,  Srinivas Swaminathan ,  Belal Helal

    IPC: G06F13/42 ,  H04B1/38 ,  H04B1/04

    CPC classification number: G06F13/4291 ,  H04B1/38 ,  H04B1/0483

    Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

    Methods and systems for data transmission
    9.
    发明授权
    Methods and systems for data transmission 有权

    公开(公告)号：US11245493B2

    公开(公告)日：2022-02-08

    申请号：US17108386

    申请日：2020-12-01

    Applicant: MARVELL ASIA PTE, LTD.

    Inventor： Benjamin P. Smith ,  Jamal Riani ,  Arash Farhoodfar ,  Sudeep Bhoja

    IPC: H04L1/00 ,  H03M13/19 ,  H03M13/25 ,  H03M13/29 ,  H04L1/06 ,  H04L27/26

    Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.

    Soft FEC With Parity Check
    10.
    发明公开
    Soft FEC With Parity Check 审中-公开

    公开(公告)号：US20230327806A1

    公开(公告)日：2023-10-12

    申请号：US18210823

    申请日：2023-06-16

    Applicant: Marvell Asia Pte Ltd

    Inventor： Jamal RIANI ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

    IPC: H04L1/00

    CPC classification number: H04L1/0071 ,  H04L1/0055 ,  H04L1/0063 ,  H04L1/0042 ,  H04L1/0046

    Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

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