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    Soft FEC with parity check
    1.
    发明授权
    Soft FEC with parity check 有权

    公开(公告)号：US12101186B2

    公开(公告)日：2024-09-24

    申请号：US18210823

    申请日：2023-06-16

    Applicant: Marvell Asia Pte Ltd

    Inventor： Jamal Riani ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

    IPC: H04L1/00 ,  H04L25/06

    CPC classification number: H04L1/0071 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0045 ,  H04L1/0046 ,  H04L1/0055 ,  H04L1/0063 ,  H04L25/067

    Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

    Near-end Crosstalk Mitigation in a SerDes Device
    2.
    发明公开
    Near-end Crosstalk Mitigation in a SerDes Device 审中-公开

    公开(公告)号：US20240305332A1

    公开(公告)日：2024-09-12

    申请号：US18596846

    申请日：2024-03-06

    Applicant: Marvell Asia Pte Ltd

    Inventor： Junyi Xu ,  Jamal Riani ,  Zuoen Wang ,  Xing Wu

    IPC: H04B3/32

    CPC classification number: H04B3/32

    Abstract: A communication apparatus includes a receiver disposed in proximity to a transmitter, and a crosstalk cancellation circuit. The receiver includes an input buffer, a front end, and an adaptive resampling circuit. The input buffer receives from the transmitter aggressor data, the aggressor data being timed by a transmitter clock clocking the transmitter. The front end receives data over a communication link, the data being serialized according to a receiver clock clocking the receiver, the receiver clock operating independently of the transmitter clock. The front end further generates a stream of data samples corresponding to the received data. The adaptive resampling circuit resamples the aggressor data, and generates resampled data timed by the receiver clock. The crosstalk cancellation circuit estimates, based on the resampled data, a crosstalk error signal related to the aggressor data, and subtracts the estimated crosstalk error signal from the stream of data samples.

    Systems and methods for timing recovery with bandwidth extension
    3.
    发明授权
    Systems and methods for timing recovery with bandwidth extension 有权

    公开(公告)号：US11831747B2

    公开(公告)日：2023-11-28

    申请号：US17589159

    申请日：2022-01-31

    Applicant: MARVELL ASIA PTE LTD.

    Inventor： Benjamin Smith ,  Jamal Riani

    IPC: H04L7/00 ,  H04L1/20

    CPC classification number: H04L7/0062 ,  H04L1/205 ,  H04L7/0029 ,  H04L7/0087

    Abstract: A receiver includes a feed-forward equalizer, a first detector, a jitter estimation circuit, and a jitter mitigation circuit. The feed-forward equalizer is configured to equalize channel gain of digitized samples of a received signal and to output equalized samples. The first detector is configured to detect symbols in the equalized samples. The jitter estimation circuit is configured to estimate jitter in the equalized samples by estimating a deviation in periodicity between pairs of the equalized samples. The jitter mitigation circuit comprises a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference.

    Tracking of sampling phase in a receiver device
    4.
    发明授权
    Tracking of sampling phase in a receiver device 有权

    公开(公告)号：US12120210B2

    公开(公告)日：2024-10-15

    申请号：US17993776

    申请日：2022-11-23

    Applicant: Marvell Asia Pte Ltd

    Inventor： Basel Alnabulsi ,  Yu Liao ,  Benjamin Smith ,  Jamal Riani

    IPC: H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/0012 ,  H04L7/033

    Abstract: An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.

    Systems and methods for Nyquist error correction
    7.
    发明授权
    Systems and methods for Nyquist error correction 有权

    公开(公告)号：US11368170B1

    公开(公告)日：2022-06-21

    申请号：US17244259

    申请日：2021-04-29

    Applicant: Marvell Asia Pte, Ltd.

    Inventor： Benjamin P. Smith ,  Jamal Riani

    IPC: H03M13/45 ,  H03M13/11 ,  H03M13/37 ,  H03M13/25 ,  H03M13/00

    Abstract: The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

    Systems and methods for interleaved hamming encoding and decoding
    8.
    发明授权
    Systems and methods for interleaved hamming encoding and decoding 有权

    公开(公告)号：US11356122B2

    公开(公告)日：2022-06-07

    申请号：US16818864

    申请日：2020-03-13

    Applicant: Marvell Asia Pte Ltd.

    Inventor： Benjamin Smith ,  Volodymyr Shvydun ,  Jamal Riani ,  Ilya Lyubomirsky

    IPC: H03M13/00 ,  H03M13/27 ,  H03M13/15

    Abstract: A communication device includes a first alignment circuit configured to receive, from a host device, a first encoded data stream including a plurality of symbols encoded with a first type of error correction code. The first alignment circuit is configured to output an aligned first encoded data stream that is aligned to boundaries between the plurality of symbols encoded with the first type of error correction code. An interleaver is configured to interleave the plurality of symbols of the aligned first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. An encoder is configured to generate, for each of the symbol sections, a parity block corresponding to the symbols in the symbol section and to output a second encoded data stream including the aligned first encoded data stream and the parity block.

    Methods and systems for data transmission
    9.
    发明授权
    Methods and systems for data transmission 有权

    公开(公告)号：US11245493B2

    公开(公告)日：2022-02-08

    申请号：US17108386

    申请日：2020-12-01

    Applicant: MARVELL ASIA PTE, LTD.

    Inventor： Benjamin P. Smith ,  Jamal Riani ,  Arash Farhoodfar ,  Sudeep Bhoja

    IPC: H04L1/00 ,  H03M13/19 ,  H03M13/25 ,  H03M13/29 ,  H04L1/06 ,  H04L27/26

    Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.

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