公开(公告)号：US5515386A

公开(公告)日：1996-05-07

申请号：US311727

申请日：1994-09-23

申请人： Yuji Takizawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Kazuyuki Tajima ,  Satomi Ikeda

发明人： Yuji Takizawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Kazuyuki Tajima ,  Satomi Ikeda

IPC分类号： H04L12/951 ,  H04Q11/04 ,  G06F11/00

CPC分类号： H04Q11/0478 ,  H04L49/40 ,  H04L2012/5616 ,  H04L2012/5646 ,  H04L49/557

摘要： A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern. The transmission circuit includes a first output circuit for outputting the normal cell data, an error correcting code generator for generating the second data based on the first data of the normal cell data supplied from the first output circuit, a second output circuit for outputting the first and second data of the idle cell data, a scrambler for scrambling the third data of the normal cell data supplied from the first output circuit, and a selector for selecting one of the first output circuit, the error correcting code generator, the second output circuit and the scrambler in accordance with a predetermined order, so that the normal cell data and the idle cell data are output from the selector.

摘要翻译： 发送电路通过通信线路发送正常小区数据和空闲小区数据。 发送空闲小区数据以填充不存在要发送的正常数据的通信线路中的每个正常小区数据和包括第一数据，第二数据和第三数据的空闲小区数据的时隙。 正常小区数据的第一，第二和第三数据分别表示目的地，第一数据的纠错码和期望信息。 空闲小区数据的第一和第二数据具有预定的比特模式，并且空闲小区数据的第三数据可以具有任何任意的比特模式。 发送电路包括用于输出正常小区数据的第一输出电路，用于根据从第一输出电路提供的正常小区数据的第一数据产生第二数据的纠错码发生器，用于输出第一 和空闲单元数据的第二数据，用于加扰从第一输出电路提供的正常单元数据的第三数据的加扰器，以及用于选择第一输出电路，纠错码产生器，第二输出电路 和加扰器，以便从选择器输出正常小区数据和空闲小区数据。

公开(公告)号：US5408476A

公开(公告)日：1995-04-18

申请号：US16871

申请日：1993-02-11

申请人： Masaaki Kawai ,  Masayoshi Sekido ,  Yuji Takizawa ,  Hidetoshi Naito ,  Satomi Ikeda ,  Kazuyuki Tajima ,  Haruo Yamashita ,  Hideo Tatsuno

发明人： Masaaki Kawai ,  Masayoshi Sekido ,  Yuji Takizawa ,  Hidetoshi Naito ,  Satomi Ikeda ,  Kazuyuki Tajima ,  Haruo Yamashita ,  Hideo Tatsuno

IPC分类号： H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H04L1/00 ,  G06F11/10

CPC分类号： H03M13/151 ,  H03M13/09

摘要： A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

摘要翻译： 提供了一种基于CRC计算的1位纠错电路，其具有确定m位的输入并行数据并且已经从n个m位串行数据转换的校正子生成电路。 1位错误检测电路循环地将余数提供给余数计算电路，并解码从该循环电源获得的余数数据，并检测1位错误。 实际数据再现电路计算校正子产生电路的第1个差分第n个寄存器的预定寄存器的输出数据与提供给预定寄存器的数据的异或，并获得作为实际数据的并行数据。 一种校正电路，其计算从实际数据再现电路获得的并行数据的异或和由1位错误检测电路检测的1位错误数据，并输出校正数据。

公开(公告)号：US5257311A

公开(公告)日：1993-10-26

申请号：US876417

申请日：1992-04-30

申请人： Hidetoshi Naito ,  Masaaki Kawai ,  Hisako Watanabe ,  Yuji Takizawa ,  Kazuyuki Tajima ,  Haruo Yamashita

发明人： Hidetoshi Naito ,  Masaaki Kawai ,  Hisako Watanabe ,  Yuji Takizawa ,  Kazuyuki Tajima ,  Haruo Yamashita

IPC分类号： H04Q3/52 ,  H04L12/26 ,  H04L12/70 ,  H04Q3/00 ,  H04Q11/04 ,  H04L9/00

CPC分类号： H04L49/3009 ,  H04L12/2697 ,  H04L43/50 ,  H04L49/3081 ,  H04L49/555 ,  H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5652 ,  H04L49/30

摘要： A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI value in the information field is compared with a VPI value in the header of the test cell when examining the test cell.

公开(公告)号：US5265088A

公开(公告)日：1993-11-23

申请号：US889924

申请日：1992-06-02

申请人： Yuji Takigawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Hisako Watanabe ,  Kazuyuki Tajima ,  Haruo Yamashita

发明人： Yuji Takigawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Hisako Watanabe ,  Kazuyuki Tajima ,  Haruo Yamashita

IPC分类号： H04L12/70 ,  H04Q11/04 ,  H04J3/26

CPC分类号： H04L49/107 ,  H04L49/3009 ,  H04L49/309 ,  H04L49/555 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5625 ,  H04L49/30

摘要： A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit. The interface unit has a reception port for receiving an ATM cell or inserting a monitor cell, and a transmission port for transferring the ATM cell or extracting the monitor cell; The multiplexer is operatively connected to corresponding interface unit for multiplexing the monitor cell; The VPI conversion tables is operatively connected to corresponding multiplexer for converting the VPI to change a transmission route of the monitor cell; The switch unit is operatively connected to the VPI conversion tables for switching the transmission route of the monitor cell based on the VPI; The demultiplexer is operatively connected to the switch unit for demultiplexing the monitor cell and transferring the monitor cell to the transmission port; The loop-back unit is operatively connected to corresponding interface unit for changing the transmission route so as to transfer the monitor cell to the same interface unit which the monitor cell is inserted, and as a result, the apparatus can be monitored by comparing the inserted monitor cell with the extracted monitor cell in the same interface unit.

公开(公告)号：US08805199B2

公开(公告)日：2014-08-12

申请号：US13301149

申请日：2011-11-21

申请人： Kazuyuki Tajima ,  Tomohiro Hashiguchi ,  Yutaka Takita

发明人： Kazuyuki Tajima ,  Tomohiro Hashiguchi ,  Yutaka Takita

IPC分类号： H04B10/12 ,  H04B10/2525

CPC分类号： H04B10/25253

摘要： A dispersion compensation design system includes a changing unit setting a changed value for the amount of dispersion compensation for a span connecting nodes constituting an optical network; a path classification unit determining whether respective paths in the optical network are capable of transmission with the changed value and classifying one or more of the paths as second category paths based on the determination results; an updating unit updating the amount of dispersion compensation with the changed value if the number of the second category paths in the latest classification result is less than the number of the second category paths in the retained previous classification result; and a repeating unit that, if not all of the paths in the optical network are capable of transmission, prevents use of combinations of amounts of dispersion compensation applied to the spans in the second category paths in the latest classification result.

摘要翻译： 色散补偿设计系统包括：改变单元，设置用于构成光网络的节点的跨度的色散补偿量的变化值; 路径分类单元，确定光网络中的相应路径是否能够以改变的值传输，并且基于确定结果将一个或多个路径分类为第二类别路径; 如果最新分类结果中的第二类别路径的数量少于所保留的先前分类结果中的第二类别路径的数量，则更新单元用改变的值更新色散补偿量; 以及如果不是全部光网络中的路径能够传输的重复单元，则防止在最新分类结果中使用在第二类别路径中应用于跨度的色散补偿量的组合。

公开(公告)号：US08781329B2

公开(公告)日：2014-07-15

申请号：US13363917

申请日：2012-02-01

申请人： Yutaka Takita ,  Tomohiro Hashiguchi ,  Kazuyuki Tajima

发明人： Yutaka Takita ,  Tomohiro Hashiguchi ,  Kazuyuki Tajima

IPC分类号： H04J14/02 ,  H04B10/12

CPC分类号： H04B10/275 ,  H04B10/25253 ,  H04J14/02

摘要： A dispersion compensation design system includes a segment dividing unit to divide an optical network into segments of a linear network or a ring network, a path classifying unit to classify one of paths of the optical network, as a specific type path, the one of the paths being incapable of transmitting an optical signal and contained in a longer path having a route longer than that of the one of the paths and capable of transmitting the optical signal, a segment reconfiguration unit to reconfigure the segments so as to maximize a number of the specific type paths, a dispersion compensation amount computing unit to compute a dispersion compensation amount in any of spans of the optical network so as to minimize the number of the specific type paths within the reconfigured segment, and an update unit to update the dispersion compensation amount with the computed dispersion compensation amount.

摘要翻译： 色散补偿设计系统包括一个分段单元，用于将光网络划分为线性网络或环网的分段，路径分类单元将光网络中的一条路径分类为特定类型路径， 路径不能发送光信号并且包含在具有比该一个路径的路径长的路径的较长路径中并且能够发送光信号的段重配置单元，以重新配置段，以便最大化 特定类型路径，色散补偿量计算单元，用于计算光网络中的任一跨度的色散补偿量，以便最小化重配置段内的特定类型路径的数量;以及更新单元，用于更新色散补偿量 与计算的色散补偿量。

公开(公告)号：US07761006B2

公开(公告)日：2010-07-20

申请号：US11808911

申请日：2007-06-13

申请人： Toru Katagiri ,  Kazuyuki Tajima ,  Tomohiro Hashiguchi

发明人： Toru Katagiri ,  Kazuyuki Tajima ,  Tomohiro Hashiguchi

IPC分类号： H04B10/20 ,  H04L12/28

CPC分类号： H04J14/0227 ,  H04B10/275 ,  H04J14/0241 ,  H04J14/0283 ,  H04J14/0284 ,  H04J14/0286

摘要： An appropriate ring topology is selected by searching network topology information on the basis of given information about client signal paths on a predetermined condition, and a wavelength ring accommodating the client signal paths and having an optimal transmission characteristic is designed on the basis of the selected ring topology. Accordingly, accommodation of client signal paths in an optical network is efficiently designed.

摘要翻译： 通过在预定条件下，基于关于客户信号路径的给定信息搜索网络拓扑信息来选择适当的环形拓扑，并且基于所选择的环设计容纳客户端信号路径并具有最佳传输特性的波长环 拓扑。 因此，有效地设计了光网络中的客户端信号路径的适应。

公开(公告)号：US20090220241A1

公开(公告)日：2009-09-03

申请号：US12395709

申请日：2009-03-01

申请人： Toru KATAGIRI ,  Tomohiro Hashiguchi ,  Yutaka Takita ,  Kazuyuki Tajima ,  Motoyoshi Sekiya ,  Takashi Toyomaki

发明人： Toru KATAGIRI ,  Tomohiro Hashiguchi ,  Yutaka Takita ,  Kazuyuki Tajima ,  Motoyoshi Sekiya ,  Takashi Toyomaki

IPC分类号： H04J14/02

CPC分类号： H04B10/25133 ,  H04J14/0221

摘要： A residual chromatic dispersion target value at a terminal node is set for each wavelength path, and also, candidates of a dispersion compensation amount settable in each chromatic dispersion compensation module on an optical network are set, and further, computation processing is executed for selecting the dispersion compensation amount in each chromatic dispersion compensation module from the candidates so that the sum of errors between the residual chromatic dispersion amounts and the set residual chromatic dispersion target values at the terminal nodes for all of wavelength paths becomes minimum. As a result, for each wavelength path on the optical network, the dispersion compensation amount in each chromatic dispersion compensation module can be designed in optimum so as to satisfy the desired optical signal quality at the terminal node, while considering the residual chromatic dispersion during the transmission.

摘要翻译： 针对每个波长路径设置终端节点的残留色散目标值，并且设置在光网络上的每个色散补偿模块中可设置的色散补偿量的候选，并且还执行计算处理以选择 每个色散补偿模块中的色散补偿量，使得残留色散量与所有波长路径的终端节点处的残留色散目标值之间的误差之和变得最小。 结果，对于光网络上的每个波长路径，可以将每个色散补偿模块中的色散补偿量最优地设计成在终端节点处满足期望的光信号质量，同时考虑到在 传输。

公开(公告)号：US20090185805A1

公开(公告)日：2009-07-23

申请号：US12235166

申请日：2008-09-22

申请人： Tomohiro Hashiguchi ,  Toru Katagiri ,  Kazuyuki Tajima ,  Takashi Toyomaki

发明人： Tomohiro Hashiguchi ,  Toru Katagiri ,  Kazuyuki Tajima ,  Takashi Toyomaki

IPC分类号： H04B10/20

CPC分类号： H04J14/0227 ,  H04J14/0246 ,  H04J14/025 ,  H04J14/0284 ,  H04L41/145 ,  H04Q11/0062 ,  H04Q2011/0086 ,  H04Q2213/1301

摘要： A network design apparatus designs arrangement of various types of optical transmission devices in stations within a linear section in a network. An acquisition unit acquires information concerning the type of optical transmission device to be provided in the stations, and information concerning cost and transmission degradation for the optical transmission devices. The designing unit designs, based on the information acquired by the acquisition unit, an arrangement for which transmission degradation between stations respectively including an optical transmission device applicable as an optical regenerative repeater, is less than or equal to a threshold, and also has the least cost. An output unit outputs information concerning the arrangement designed by the design unit.

摘要翻译： 网络设计装置在网络中的线性部分内的站内设计各种类型的光传输设备的布置。 获取单元获取关于要在站中提供的光传输设备的类型的信息，以及关于光传输设备的成本和传输劣化的信息。 设计单元基于由采集单元获取的信息，设计分别包括可用作光学再生中继器的光传输设备的站之间的传输劣化小于或等于阈值的布置，并且还具有最小 成本。 输出单元输出关于由设计单元设计的布置的信息。

公开(公告)号：US20080164913A1

公开(公告)日：2008-07-10

申请号：US11979679

申请日：2007-11-07

申请人： Manabu Hirata ,  Takashi Taya ,  Kazuyuki Tajima

发明人： Manabu Hirata ,  Takashi Taya ,  Kazuyuki Tajima

IPC分类号： G01R19/00

CPC分类号： H03F3/45

摘要： A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

摘要翻译： 峰值保持电路包括具有作为差分对的第一和第二晶体管的差分放大器，第一晶体管在其栅极接收输入信号，连接在第一电源和连接第二晶体管的栅极的输出节点之间的第三晶体管 连接在输出节点和第二电源之间的用于保持峰值电压的电容器，与电容器并联连接的用于放电的电阻器，以及 第四晶体管并联连接到第一晶体管，第四晶体管在其栅极处接收用于限制电压的参考电压。