公开(公告)号：US20050151567A1

公开(公告)日：2005-07-14

申请号：US10506641

申请日：2003-03-06

申请人： Masaaki Shimada ,  Tomoyasu Yamada ,  Keiichi Sekiguchi

发明人： Masaaki Shimada ,  Tomoyasu Yamada ,  Keiichi Sekiguchi

IPC分类号： G01R19/04 ,  G01R19/165 ,  H03K5/153

CPC分类号： G01R19/16538 ,  G01R19/04

摘要： An AC voltage generated by an AC power source 1 is rectified by a full-wave rectifying circuit 2, which generates a rectified voltage. An internal regulator 33 performs waveform shaping of the rectified voltage. A comparator 42 compares the rectified voltage output from the internal regulator 33 with a reference voltage V1 and detects a period in which the rectified voltage exceeds the reference voltage V1. According to an output signal of the comparator 42, a determination signal generation circuit 50 determines the power source voltage supplied form the AC power source 1 and generates a determination signal. Accordingly, there is no need of a capacitor, etc. for detecting the peak value of the rectified voltage, and it is possible to reduce the size and cost of an AC voltage detection circuit.

摘要翻译： 由交流电源1产生的交流电压由全波整流电路2整流，产生整流电压。 内部稳压器33对整流电压进行波形整形。 比较器42将来自内部调节器33的整流电压与参考电压V 1进行比较，并检测整流电压超过参考电压V 1的周期。根据比较器42的输出信号，确定信号产生电路 50确定从AC电源1提供的电源电压并产生确定信号。 因此，不需要用于检测整流电压的峰值的电容器等，并且可以减小AC电压检测电路的尺寸和成本。

公开(公告)号：US07271579B2

公开(公告)日：2007-09-18

申请号：US10506641

申请日：2003-03-06

申请人： Masaaki Shimada ,  Tomoyasu Yamada ,  Keiichi Sekiguchi

发明人： Masaaki Shimada ,  Tomoyasu Yamada ,  Keiichi Sekiguchi

IPC分类号： G01R19/22

CPC分类号： G01R19/16538 ,  G01R19/04

摘要： An AC voltage generated by an AC power source 1 is rectified by a full-wave rectifying circuit 2, which generates a rectified voltage. An internal regulator 33 performs waveform shaping of the rectified voltage. A comparator 42 compares the rectified voltage output from the internal regulator 33 with a reference voltage V1 and detects a period in which the rectified voltage exceeds the reference voltage V1. According to an output signal of the comparator 42, a determination signal generation circuit 50 determines the power source voltage supplied form the AC power source 1 and generates a determination signal. Accordingly, there is no need of a capacitor, etc. for detecting the peak value of the rectified voltage, and it is possible to reduce the size and cost of an AC voltage detection circuit.

摘要翻译： 由交流电源1产生的交流电压由全波整流电路2整流，产生整流电压。 内部稳压器33对整流电压进行波形整形。 比较器42将来自内部调节器33的整流电压与参考电压V 1进行比较，并检测整流电压超过参考电压V 1的周期。 根据比较器42的输出信号，确定信号生成电路50确定从AC电源1提供的电源电压，并产生确定信号。 因此，不需要用于检测整流电压的峰值的电容器等，并且可以减小AC电压检测电路的尺寸和成本。

公开(公告)号：US07639516B2

公开(公告)日：2009-12-29

申请号：US11284986

申请日：2005-11-21

申请人： Hiroshi Usui ,  Tomoyasu Yamada ,  Masaaki Shimada

发明人： Hiroshi Usui ,  Tomoyasu Yamada ,  Masaaki Shimada

IPC分类号： H02M3/335

CPC分类号： H02M3/33507

摘要： The ON duration of an N channel MOS transistor is set based on a target voltage at a node between a resistor and a light receiving element of a photocoupler. A comparator compares the target voltage with a reference voltage at a node between a variable resistor and a resistor. A normal mode and a low frequency operation mode are switched from one to the other based on an output signal from the comparator. The resistance of the variable resistor becomes low when an input voltage from a power source is high. Even when the input voltage is high, therefore, the ON duration of the N channel MOS transistor at the transition between the normal mode and the low frequency operation mode becomes short. This reduces the switching energy in low frequency operation mode, thereby suppressing noise.

摘要翻译： 基于光电耦合器的电阻器和光接收元件之间的节点处的目标电压来设定N沟道MOS晶体管的导通时间。 比较器将目标电压与可变电阻和电阻之间的节点处的参考电压进行比较。 基于来自比较器的输出信号，正常模式和低频操作模式从一个切换到另一个。 当电源的输入电压高时，可变电阻器的电阻变低。 因此即使在输入电压高的情况下，在正常模式与低频工作模式之间的转换时，N沟道MOS晶体管的导通时间变短。 这降低了低频操作模式中的开关能量，从而抑制噪声。

公开(公告)号：US07272018B2

公开(公告)日：2007-09-18

申请号：US10538440

申请日：2003-12-09

申请人： Tomoyasu Yamada ,  Masaaki Shimada

发明人： Tomoyasu Yamada ,  Masaaki Shimada

IPC分类号： H02M3/335

CPC分类号： H02M1/4208 ,  H02M2001/0032 ,  Y02B70/126 ,  Y02B70/16 ,  Y02P80/112

摘要： By an NMOS (22) being switched on or off, a direct-current voltage E0 is charged in a capacitor (24), and a DC/DC converting circuit (30) charges a direct-current output voltage V0 to be supplied to a load L in a capacitor (34). A load state detection circuit (40) determines whether the load L is in a lightly loaded state or in a non-lightly loaded state, and outputs a signal (S40) as a determination signal. When the load state detection circuit (40) outputs a signal (S41) of “L” as a signal representing that it is a lightly loaded state, a time period setting circuit (41) outputs a signal (S41) of “L” after a preset time period elapses. A PFC on/off switching circuit (42) is supplied with the signal (S41) of “L”, and outputs a control signal (S25) of “L” to a power factor improvement circuit (20). Accordingly, in the case where the load L enters a lightly loaded state, the operation of the power factor improvement circuit (20) is stopped when the preset time elapses.

摘要翻译： 通过接通或断开的NMOS（22），在电容器（24）中充电直流电压E ，并且DC / DC转换电路（30）对直流电 输出电压V 0 <0>被提供给电容器34中的负载L. 负载状态检测电路（40）判定负载L是处于轻负载状态还是处于非轻负载状态，并输出信号（S40）作为判定信号。 当负载状态检测电路（40）输出“L”的信号（S41）作为表示轻载状态的信号时，时段设定电路（41）输出“S” “经过预设时间段。 PFC导通/截止开关电路（42）被提供有“L”的信号（S 41），并将一个“L”的控制信号（S25）输出到功率因数改善电路（20）。 因此，在负载L进入轻负载状态的情况下，当经过预设时间时，功率因数改善电路20的动作停止。

公开(公告)号：US20050018458A1

公开(公告)日：2005-01-27

申请号：US10496161

申请日：2002-11-28

申请人： Masaaki Shimada ,  Tomoyasu Yamada

发明人： Masaaki Shimada ,  Tomoyasu Yamada

IPC分类号： H02M1/00 ,  H02M1/42 ,  H02M7/00

CPC分类号： H02M1/4225 ,  H02M2001/0025 ,  Y02B70/126

摘要： A switching power supply such that the step-up ratio of when the power-factor is improved does not increase, and the conversion efficiency can be improved. In a case where the error voltage Ver outputted from a conductance amplifier (23) increases over a reference voltage Vref2, a switching signal of high level is outputted from a comparator (59) to a FET (57) to turn on the FET (57). Therefore a resistor (56) is bypassed, and as a result a reference voltage Vref1 inputted into the conductance amplifier (23) is changed from a reference voltage Vrefl-1 to Vrefl-2 of lower level. Further, since the variation of the error voltage Ver outputted from the conductance amplifier (23) decreases, the output voltage Vout also decreases.

摘要翻译： 开关电源使得功率因数提高时的升压比不增加，并且可以提高转换效率。 在从电导放大器（23）输出的误差电压Ver超过参考电压Vref2的情况下，高电平的开关信号从比较器（59）输出到FET（57）以导通FET（57） ） 因此，旁路电阻（56），结果，输入到电导放大器（23）的参考电压Vref1从较低电平的参考电压Vrefl-1变为Vrefl-2。 此外，由于从电导放大器（23）输出的误差电压Ver的变化减小，所以输出电压Vout也降低。

公开(公告)号：US20060056210A1

公开(公告)日：2006-03-16

申请号：US10538440

申请日：2003-12-09

申请人： Tomoyasu Yamada ,  Masaaki Shimada

发明人： Tomoyasu Yamada ,  Masaaki Shimada

IPC分类号： H02M7/02

CPC分类号： H02M1/4208 ,  H02M2001/0032 ,  Y02B70/126 ,  Y02B70/16 ,  Y02P80/112

摘要： By an NMOS (22) being switched on or off, a direct-current voltage E0 is charged in a capacitor (24), and a DC/DC converting circuit (30) charges a direct-current output voltage V0 to be supplied to a load L in a capacitor (34). A load state detection circuit (40) determines whether the load L is in a lightly loaded state or in a non-lightly loaded state, and outputs a signal (S40) as a determination signal. When the load state detection circuit (40) outputs a signal (S41) of “L” as a signal representing that it is a lightly loaded state, a time period setting circuit (41) outputs a signal (S41) of “L” after a preset time period elapses. A PFC on/off switching circuit (42) is supplied with the signal (S41) of “L”, and outputs a control signal (S25) of “L” to a power factor improvement circuit (20). Accordingly, in the case where the load L enters a lightly loaded state, the operation of the power factor improvement circuit (20) is stopped when the preset time elapses.

摘要翻译： 通过接通或断开的NMOS（22），在电容器（24）中充电直流电压E ，并且DC / DC转换电路（30）对直流电 输出电压V 0 <0>被提供给电容器34中的负载L. 负载状态检测电路（40）判定负载L是处于轻负载状态还是处于非轻负载状态，并输出信号（S40）作为判定信号。 当负载状态检测电路（40）输出“L”的信号（S41）作为表示轻载状态的信号时，时段设定电路（41）输出“S” “经过预设时间段。 PFC导通/截止开关电路（42）被提供有“L”的信号（S 41），并将一个“L”的控制信号（S25）输出到功率因数改善电路（20）。 因此，在负载L进入轻负载状态的情况下，当经过预设时间时，功率因数改善电路20的动作停止。

公开(公告)号：US06714425B2

公开(公告)日：2004-03-30

申请号：US10244888

申请日：2002-09-16

申请人： Tomoyasu Yamada ,  Masaaki Shimada

发明人： Tomoyasu Yamada ,  Masaaki Shimada

IPC分类号： H02M3335

CPC分类号： H02M1/4225 ,  H02J2009/007 ,  H02M2001/0032 ,  H02M2001/007 ,  Y02B70/126 ,  Y02B70/16 ,  Y02P80/112

摘要： In the switching power supply, a load state judgment circuit (25) judges the state of a load (20) according to a pulse signal VG to be used for ON/OFF control of a MOS transistor (8) as a switching element in a DC—DC converter (127). In order to reduce a power consumption of the switching power supply, a PFC ON/OFF switching circuit (24) stops the operation of the power factor improving converter (126) when the judgment result indicates a light load state, and starts the operation of the power factor improving converter (126) when the judgment result indicates a heavy load state.

摘要翻译： 在开关电源中，负载状态判断电路（25）根据用于MOS晶体管（8）的ON / OFF控制的脉冲信号VG来判断负载（20）的状态，作为开关元件的开关元件 DC-DC转换器（127）。 为了降低开关电源的功耗，当判断结果表示轻负载状态时，PFC ON / OFF切换电路（24）停止功率因数改善转换器（126）的动作，开始运转 功率因数改善转换器（126），当判断结果指示重负载状态时。

公开(公告)号：US20060109692A1

公开(公告)日：2006-05-25

申请号：US11284986

申请日：2005-11-21

申请人： Hiroshi Usui ,  Tomoyasu Yamada ,  Masaaki Shimada

发明人： Hiroshi Usui ,  Tomoyasu Yamada ,  Masaaki Shimada

IPC分类号： H02M3/335

CPC分类号： H02M3/33507

摘要： The ON duration of an N channel MOS transistor is set based on a target voltage at a node between a resistor and a light receiving element of a photocoupler. A comparator compares the target voltage with a reference voltage at a node between a variable resistor and a resistor. A normal mode and a low frequency operation mode are switched from one to the other based on an output signal from the comparator. The resistance of the variable resistor becomes low when an input voltage from a power source is high. Even when the input voltage is high, therefore, the ON duration of the N channel MOS transistor at the transition between the normal mode and the low frequency operation mode becomes short. This reduces the switching energy in low frequency operation mode, thereby suppressing noise.

公开(公告)号：US06882551B2

公开(公告)日：2005-04-19

申请号：US10496161

申请日：2002-11-28

申请人： Masaaki Shimada ,  Tomoyasu Yamada

发明人： Masaaki Shimada ,  Tomoyasu Yamada

IPC分类号： H02M1/00 ,  H02M1/42 ,  H02M7/155

CPC分类号： H02M1/4225 ,  H02M2001/0025 ,  Y02B70/126

摘要： A switching power supply such that the step-up ratio of when the power-factor is improved does not increase, and the conversion efficiency can be improved. In a case where the error voltage Ver outputted from a conductance amplifier (23) increases over a reference voltage Vref2, a switching signal of high level is outputted from a comparator (59) to a FET (57) to turn on the FET (57). Therefore a resistor (56) is bypassed, and as a result a reference voltage Vref1 inputted into the conductance amplifier (23) is changed from a reference voltage Vref1-1 to Vref1-2 of lower level. Further, since the variation of the error voltage Ver outputted from the conductance amplifier (23) decreases, the output voltage Vout also decreases.

摘要翻译： 开关电源使得功率因数提高时的升压比不增加，并且可以提高转换效率。 在从电导放大器（23）输出的误差电压Ver超过参考电压Vref 2的情况下，将高电平的开关信号从比较器（59）输出到FET（57）以导通FET（57） 57）。 因此，旁路电阻（56），结果，输入到电导放大器（23）的参考电压Vref 1从基准电压Vref1-1变为低电平的Vref1〜2。 此外，由于从电导放大器（23）输出的误差电压Ver的变化减小，所以输出电压Vout也降低。

公开(公告)号：US08210948B2

公开(公告)日：2012-07-03

申请号：US11661942

申请日：2005-07-15

申请人： Masaaki Shimada ,  Tomoaki Ryu ,  Kazuhiko Nakane

发明人： Masaaki Shimada ,  Tomoaki Ryu ,  Kazuhiko Nakane

IPC分类号： A63F13/00

CPC分类号： G11B27/34 ,  G11B19/025 ,  G11B2220/2562 ,  H04N5/783 ,  H04N5/85 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/8205 ,  H04N9/8227 ,  H04N21/4126 ,  H04N21/47 ,  H04N21/4856

摘要： A portable recording medium (100) stores video contents and icon information relating to an icon picture associated with the video contents and indicative of an operation mode corresponding to user operation of the recording medium reproducing apparatus (1). The recording medium reproducing apparatus (1) includes an image display plane (8) which is a frame memory area used for displaying video data of the video contents stored in the portable recording medium (100); a memory (15, 16) which stores the icon information stored in the portable recording medium (100); an OSD plane (18) which is a frame memory area used for displaying the icon picture on the basis of the icon information stored in the memory (15, 16); and a synthesizing device (10) which synthesizes the data held in the video display plane (8) and the data held in the information display plane (18), thereby outputting a superimposed video signal.

摘要翻译： 便携式记录介质（100）存储与与视频内容相关联的图标图像相关的视频内容和图标信息，并且指示对应于记录介质再现装置（1）的用户操作的操作模式。 记录介质再现装置（1）包括作为用于显示存储在便携式记录介质（100）中的视频内容的视频数据的帧存储区域的图像显示平面（8）。 存储器（15,16），其存储存储在便携式记录介质（100）中的图标信息; OSD平面（18），其是用于基于存储在存储器（15,16）中的图标信息显示图标图像的帧存储区域; 以及合成装置（10），其将保持在视频显示平面（8）中的数据和保存在信息显示平面（18）中的数据合成，从而输出叠加的视频信号。