公开(公告)号：US20110193215A1

公开(公告)日：2011-08-11

申请号：US13023565

申请日：2011-02-09

申请人： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

发明人： Masahiro TOYAMA ,  Yutaka UEMATSU ,  Hideki OSAKA

IPC分类号： H01L23/50

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

摘要： Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.

摘要翻译： 提供了通过现实的安装方法来减小寄生电感的方法。 在半导体封装的表面层上，设置有多个梳齿形接地焊盘的接地焊盘，这些接地焊盘是用于引线接合的连接点，并且突出在半导体封装的表面层上。 在梳齿形接地垫之间设置电源垫。 两根长而短的接地线布置在一个梳齿形接地垫中。 此外，两个长短电源线布置在一个电源垫中。 通过将长接地线和长电源线布置为彼此并联并且将短电源线和短接地线布置成彼此并联并且彼此靠近，寄生电感 减少。