公开(公告)号：US5331639A

公开(公告)日：1994-07-19

申请号：US609647

申请日：1990-11-06

申请人： Masahiro Takatori ,  Yukio Nakano ,  Keiichi Ishida ,  Takashi Mori ,  Yoshihiro Ashi ,  Tadayuki Kanno ,  Hiromi Ueda

发明人： Masahiro Takatori ,  Yukio Nakano ,  Keiichi Ishida ,  Takashi Mori ,  Yoshihiro Ashi ,  Tadayuki Kanno ,  Hiromi Ueda

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04L7/00 ,  H04Q11/04

CPC分类号： H04J3/0623 ,  H04J2203/0089

摘要： A method and an apparatus for converting a frame phase of a signal having a frame structure specified in the CCITT recommendations which contains N (N: an integer 2 or above) pieces of frames applied with time-division/multiplex, in which the N pieces of frames are given to N pieces of memories, respectively, a write address is given independently to each memory so that the N pieces of frames are written in the respective memories in a same phase as the phase in the signal, a read address is given independently to each memory so that the N pieces of frames are read out of the respective memories in a same phase as the write phase, a difference between a write address and a read address in each memory is set identical under an initial state, and justification is executed for a frame which is read out of the memory in accordance with a difference between existing write address and read address in each memory, whereby to perform frame phase conversion while maintaining relative phase among respective frames.

摘要翻译： 一种用于转换具有CCITT建议中指定的帧结构的信号的帧相位的方法和装置，其包含以时分复用应用的N（N：整数2或以上）帧，其中N个 分别给予N个存储器，每个存储器独立地给出写入地址，使得N个帧以与信号中的相位相同的相位写入各个存储器中，给出读取地址 独立于每个存储器，使得N个帧在与写入相位相同的相位中从各个存储器读出，每个存储器中的写入地址和读取地址之间的差在初始状态下被设置为相同，并且对齐 根据存储器中的现有写入地址和读取地址之间的差异从存储器中读出的帧被执行，由此执行帧相位转换，同时保持相对相位 g各个框架。

公开(公告)号：US5271006A

公开(公告)日：1993-12-14

申请号：US663956

申请日：1991-03-19

申请人： Yoshihiro Ashi ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

发明人： Yoshihiro Ashi ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

IPC分类号： H04J3/06 ,  H04J3/22

CPC分类号： H04J3/0629

摘要： A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.

摘要翻译： PCT No.PCT / JP90 / 00925 Sec。 371日期1991年3月19日 102（e）1991年3月19日PCT PCT 1990年7月18日PCT公布。 公开号WO91 / 01601 日期1991年2月7日。一种帧对准器及其控制方法和系统，其中在确保TSSI（时隙序列完整性）的同时执行帧对准。 在用于发送具有高速帧中的帧结构的多个低速信号的系统中，设置用于帧对准器存储器的写入开始阶段的多个候选，并且通过访问存储写入的公共相位存储器 低速信号共享的起始相位需要存储在高速帧中的所有低速信号之间的相位匹配，从用于帧对准器存储器的写入开始相位的候选中选择写入开始相位。

公开(公告)号：US5189668A

公开(公告)日：1993-02-23

申请号：US741588

申请日：1991-08-07

申请人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Tadayuki Kanno

发明人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Tadayuki Kanno

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04L12/937

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/255 ,  H04L2012/5647 ,  H04L2012/5672 ,  H04L2012/5681

摘要： An ATM switch has a plurality of concentration space-division switches each constituted with an S-stage connection of switch modules. Each of the switch modules includes M buffers and a selector for selecting an arbitrary one of outputs from the M buffers. Each stage includes switch modules of which the number is obtained by multiplying by at most M a number of switch modules disposed in a stage succeeding thereto. The S stages include a final stage constituted with a switch module.

公开(公告)号：US5473598A

公开(公告)日：1995-12-05

申请号：US744513

申请日：1991-08-13

申请人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Tadayuki Kanno

发明人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Tadayuki Kanno

IPC分类号： H04L12/70 ,  H04L12/931 ,  H04L12/947 ,  H04J3/26

CPC分类号： H04L49/254 ,  H04L49/256 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/552 ,  H04L2012/5627

摘要： A cell routing method and apparatus in an ATM processing apparatus. The ATM processing apparatus has two or more routing tables associated with address filters of an ATM switch to store routing information for indicating the destination of cell output, and two or more conversion tables associated with VPI conversion circuits for replacing VPI (Virtual Path Identifier) or VCI conversion circuits for replacing VCI (Virtual Channel Identifier) to store information for indicating the VPI or VCI obtained after conversion. In an input interface circuit, selection information indicating which routing table and conversion table out of the above described two or more routing tables and two or more conversion tables should be selected is written into an occupied area within a cell. In a switch circuit, the selection information is read and one routing table is selected out of the above described two or more routing tables on the basis of the selection information thus read, and cell routing is thus performed based on information in the selected routing table. Further, in an output interface circuit, selection information contained in the cell is read and one conversion table is selected out of the above described two or more conversion tables on the basis of the selection information thus read, and VPI conversion or VCI conversion is thus executed based on information in the selected conversion table.

摘要翻译： 一种ATM处理装置中的小区路由方法和装置。 ATM处理装置具有与ATM交换机的地址过滤器相关联的两个或多个路由表，以存储用于指示小区输出的目的地的路由信息​​，以及与用于替换VPI（虚拟路径标识符）的VPI转换电路相关联的两个或更多个转换表， 用于替换VCI（虚拟信道标识符）的VCI转换电路以存储用于指示转换后获得的VPI或VCI的信息。 在输入接口电路中，指示应当选择上述两个或多个路由表和两个或多个转换表中的哪个路由表和转换表的选择信息被写入小区内的占用区域。 在开关电路中，读取选择信息，并且根据这样读取的选择信息，从上述两个或多个路由表中选出一个路由表，并且基于所选择的路由表中的信息执行小区路由 。 此外，在输出接口电路中，读取包含在单元中的选择信息，并且根据这样读取的选择信息从上述两个或更多个转换表中选出一个转换表，并且因此进行VPI转换或VCI转换 基于所选转换表中的信息执行。

公开(公告)号：US5128939A

公开(公告)日：1992-07-07

申请号：US507506

申请日：1990-04-11

申请人： Masahiro Takatori ,  Yukio Nakano ,  Tadayuki Kanno ,  Hiromi Ueda

发明人： Masahiro Takatori ,  Yukio Nakano ,  Tadayuki Kanno ,  Hiromi Ueda

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0623

摘要： Disclosed is a method and apparatus of phase-converting a frame, each frame containing a plurality of data, a frame synchronous signal arranged in a predetermined first relative phase position in the frame, and a pointer arranged in a predetermined second relative phase position and storing a value indicating a phase difference between the second relative phase position and the front position of the data in the frame, in which the following operations are carried out: consecutively receiving the frames; sequentially arranging a predetermined number of data among the plurality of data in the received frame in a transmission frame in accordance with a received order, and arranging the frame synchronous signal and the pointer in the received frame in the first relative phase position and the second relative phase position, the first relative phase position being independent to the second relative phase position, to form the tansmission frame; detecting a fourth relative phase position in the transmission frame, the fourth relative phase position storing a data same as a specific data arranged in a third relative phase positon in the received frame; obtaining a difference between the fourth relative phase position and the third relative phase position; and setting the difference between the value of the pointer in the received frame and the obtained phase difference as the value of the pointer in the transmission frame.

摘要翻译： 公开了一种帧相位转换的方法和装置，每帧包含多个数据，布置在帧中预定的第一相对相位位置的帧同步信号，以及布置在预定的第二相对相位位置的指针，并存储 指示执行以下操作的帧中的数据的第二相对位置与前端位置之间的相位差的值：连续接收帧; 根据接收到的顺序在传输帧中顺序排列接收到的帧中的多个数据中的预定数量的数据，并将帧同步信号和指针置于接收帧中的第一相对相位和第二相位 相位位置，第一相对相位位置独立于第二相对位置，以形成输出帧; 检测所述传输帧中的第四相对相位，所述第四相对相位位置存储与所述接收帧中的第三相位相位中布置的特定数据相同的数据; 获得所述第四相对位置与所述第三相对位置之间的差; 并且将接收到的帧中的指针的值与获得的相位差之间的差设置为发送帧中的指针的值。

公开(公告)号：US5197063A

公开(公告)日：1993-03-23

申请号：US641928

申请日：1991-01-16

申请人： Yukio Nakano ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

发明人： Yukio Nakano ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

IPC分类号： H04J3/22 ,  H04J3/00 ,  H04J3/16 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/1611

摘要： A circuit switching apparatus and method for time division network with various transmission speeds for time-division multiplexing a plurality of circuits including signals at different transmission speeds, transmitting the same onto an input highway, repeatedly recording the transmitted signals in a data memory in a predetermined order, reading respective recorded signals in a predetermined order onto an output highway. An access unit for reading signals from the data memory has an address control memory for storing circuit switching information, a circuit speed control memory for storing transmission speed information for the respective circuits and an address generating section for generating an address for accessing the data memory on the basis of the circuit switching information and the circuit transmission speed information from those memories.

摘要翻译： 一种用于具有各种传输速度的时分网络的电路交换装置和方法，用于对包括不同传输速度的信号的多个电路进行时分复用，将其发送到输入公路上，以预定的方式将数据存储器重复地记录发送的信号 以预定顺序将各个记录信号读出到输出高速公路上。 用于从数据存储器读取信号的访问单元具有用于存储电路切换信息的地址控制存储器，用于存储各个电路的传输速度信息的电路速度控制存储器和用于生成访问数据存储器的地址的地址生成部分 电路切换信息的基础和来自这些存储器的电路传输速度信息。

公开(公告)号：US5206858A

公开(公告)日：1993-04-27

申请号：US747137

申请日：1991-08-19

申请人： Yukio Nakano ,  Takashi Mori ,  Tadayuki Kanno

发明人： Yukio Nakano ,  Takashi Mori ,  Tadayuki Kanno

IPC分类号： H04J3/16 ,  H04L12/951 ,  H04L12/953 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04J3/1617 ,  H04J2203/0089 ,  H04L2012/5672

摘要： A method of mapping a virtual container multiplexed with a pointer indicating a first bit position in a transmission frame onto an asynchronous transfer mode cell and transmitting the virtual container thus converted. The method includes the steps of deriving a first bit position of the virtual container in the transmission frame from the value of the pointer of the virtual container, mapping the virtual container onto information fields of cells, deriving a first bit position of the virtual container within a cell information field of the asynchronous transfer mode cell from the first bit position information in the frame, and writing the first bit position information within the cell information field and information contained in the pointer into a field which has a fixed phase relationship with respect to a cell header and transmitting the cells.

摘要翻译： 一种将与指示传输帧中的第一比特位置的指针复用的虚拟容器映射到异步传输模式小区并发送如此转换的虚拟容器的方法。 该方法包括以下步骤：从虚拟容器的指针的值导出传输帧中的虚拟容器的第一比特位置，将虚拟容器映射到小区的信息字段，导出虚拟容器的第一比特位置 根据帧中的第一比特位置信息，异步传送模式信元的小区信息字段，将小区信息字段内的第一比特位置信息和包含在指针中的信息写入相对于 一个单元格标题并传送单元。

公开(公告)号：US5018135A

公开(公告)日：1991-05-21

申请号：US412475

申请日：1989-09-26

申请人： Yoshihiro Ashi ,  Tadayuki Kanno

发明人： Yoshihiro Ashi ,  Tadayuki Kanno

IPC分类号： H04J3/06 ,  H04J3/08

CPC分类号： H04J3/08 ,  H04J3/0685

摘要： The present invention relates to an add drop multiplexer related to the synchronous multiplexing method, and includes a pass-through line connecting unit, which is driven by a timing signal extracted from a signal received through a transmission line and effects branching and insertion of the line as well as connection of pass-through lines at multiplexed levels; an office line connecting unit having an office interface function for each of other devices in a same office; a first frame aligner connecting multiplex branched signals from the pass-through line connecting unit with the office line connecting unit; and a second frame aligner connecting multiplex inserted signals from the office line connecting unit with the pass-through line connecting unit. In this way, since the whole pass-through line connecting unit can be driven only with the timing signal extracted from the received signal from the transmission line and the frame aligner can be removed from the path of the signal through the pass-through lines, it is possible to reduce the signal delay in the pass-through lines within the add drop multiplexer.

摘要翻译： 本发明涉及一种与同步多路复用方法相关的分插复用器，并且包括一个直通线连接单元，该直通线连接单元由从通过传输线接收的信号中提取的定时信号驱动，并实现线路的分支和插入 以及多路复用级别的直通线路的连接; 具有用于同一办公室中的每个其他设备的办公室接口功能的办公室线路连接单元; 第一框架对准器，其将来自所述直通线连接单元的多路分支信号与所述办公室线路连接单元连接; 以及第二框架对准器，其将来自办公室线路连接单元的多路插入信号与直通线连接单元连接。 以这种方式，由于只能通过从传输线从接收信号中提取的定时信号来驱动整个直通线连接单元，并且可以通过直通线从信号的路径移除帧对准器， 可以减小加法分路复用器内的直通线路中的信号延迟。

公开(公告)号：US4858224A

公开(公告)日：1989-08-15

申请号：US140791

申请日：1988-01-05

申请人： Yukio Nakano ,  Tadayuki Kanno

发明人： Yukio Nakano ,  Tadayuki Kanno

IPC分类号： H04M3/26 ,  H04J3/14 ,  H04L29/14 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/14

摘要： In a digital switching equipment or a digital cross-connect equipment including a plurality of receiving circuits, a multiplexer, a time division switch, a demultiplexer, and a plurality of transmitting circuits, each of the receiving circuits or the multiplexer has a circuit to insert a specific sequence into filling time slots of a plurality of subhighways of a highway having a plurality of time slots and each of the transmitting circuits and the demultiplexer has a circuit to detect the specific sequence inserted into the filling time slots such that when either one of the error detect circuits detects an error, a route change of the filling time slots is accomplished by means of a time division switch so as to predict a location of occurrence of a failure depending on a change in a detection state of the error detect circuits in association with the route change.

摘要翻译： 在包括多个接收电路的数字交换设备或数字交叉连接设备中，多路复用器，时分开关，解复用器和多个发送电路，每个接收电路或复用器具有插入的电路 具有多个时隙的高速公路的多个高速公路的填充时隙的特定顺序，并且每个发送电路和多路分解器具有检测插入到填充时隙中的特定序列的电路，使得当任何一个 错误检测电路检测到错误，通过时分开关来实现填充时隙的路线变化，以便根据错误检测电路的检测状态的变化来预测故障发生的位置 与路线变化的关联。