公开(公告)号：US4841172A

公开(公告)日：1989-06-20

申请号：US225495

申请日：1988-07-28

Applicant: Masaji Ueno ,  Hideaki Masuoka

Inventor： Masaji Ueno ,  Hideaki Masuoka

IPC: H03K17/04 ,  H03K17/66 ,  H03K19/00 ,  H03K19/013 ,  H03K19/017 ,  H03K19/08 ,  H03K19/088

CPC classification number: H03K19/0136 ,  H03K19/0013 ,  H03K19/01721

Abstract: A logic circuit comprises a current control means including first and second MOS transistors for controlling the current to the output circuit and also for controlling the output wave form, in accordance with the input signal and the output signal. When the output signal rises from a low level to a high level, a large current is supplied to the output circuit to get a steep rise. When the output signal is high level, the current to the output circuit becomes small, and the power consumption is reduced.

公开(公告)号：US08115558B2

公开(公告)日：2012-02-14

申请号：US12726474

申请日：2010-03-18

Applicant: Yuki Tsuda ,  Hideaki Masuoka

Inventor： Yuki Tsuda ,  Hideaki Masuoka

IPC: H03L7/099 ,  H03L7/087 ,  H03B5/12 ,  H03C3/22

CPC classification number: H03L7/099 ,  H03L7/087 ,  H03L7/10

Abstract: A digital PLL circuit includes: an oscillation circuit, wherein an oscillation frequency is controlled by changing the number of capacitance elements to be connected in parallel to an inductance element; and a phase comparator part configured to perform a digital phase comparison of a reference clock and a delayed clock thereof, with an oscillation circuit output; and based on the comparison result, to control the number of the capacitance elements so as to bring the phase of the oscillation circuit output closer to the reference clock phase, wherein the capacitance element includes: a coarse adjustment capacitor configured to have a predetermined capacitance; and fine adjustment capacitors configured to have a capacitance of 1/n of that of the coarse adjustment capacitor, wherein a predetermined number of the fine adjustment capacitors function as one coarse adjustment capacitor at the time of coarse adjustment.

Abstract translation: 数字PLL电路包括：振荡电路，其中通过将要并联的电容元件的数量改变为电感元件来控制振荡频率; 以及相位比较器部，被配置为利用振荡电路输出执行基准时钟及其延迟时钟的数字相位比较; 并且基于比较结果，控制电容元件的数量，使振荡电路的输出相位相对于基准时钟相位更接近，其中，电容元件包括：配置为具有预定电容的粗调电容器; 以及微调电容器，其被配置为具有所述粗调电容器的电容的1 / n的电容，其中预定数量的微调电容器在粗调时用作一个粗调电容器。

公开(公告)号：US5488330A

公开(公告)日：1996-01-30

申请号：US361583

申请日：1994-12-22

Applicant: Hideaki Masuoka ,  Akio Kuroda

Inventor： Hideaki Masuoka ,  Akio Kuroda

IPC: H03G11/00 ,  H03D7/14 ,  H03F1/32 ,  H03F3/45 ,  H04B1/26

CPC classification number: H03F3/4521 ,  H03F1/3211 ,  H03F3/45085 ,  H03F3/45089 ,  H03F2203/45366 ,  H03F2203/45542 ,  H03F2203/45544 ,  H03F2203/45574 ,  H03F2203/45702

Abstract: A first differential amplifier includes first and second transistors. A bias circuit includes a second differential amplifier, a constant-current source, and a capacitor. The bases of third and fourth transistors constituting a second differential amplifier, are connected to those of the first and second transistors, respectively. The constant-current source supplies a constant current to the third and fourth transistors, and one end of the capacitor is connected to a connection node of the constant-current source and fourth transistor. In the bias circuit, when a high-level signal is supplied to the base of the first transistor, the capacitor is charged and discharged in accordance with the operations of the third and fourth transistors, with the result that the base potential of the first and second transistors is stabilized, and the operation current flowing through the first differential amplifier is prevented from increasing.

Abstract translation: 第一差分放大器包括第一和第二晶体管。 偏置电路包括第二差分放大器，恒流源和电容器。 构成第二差分放大器的第三和第四晶体管的基极分别连接到第一和第二晶体管的基极。 恒流源向第三和第四晶体管提供恒定电流，并且电容器的一端连接到恒流源和第四晶体管的连接节点。 在偏置电路中，当向第一晶体管的基极提供高电平信号时，根据第三和第四晶体管的操作对电容器进行充电和放电，结果是第一和第二晶体管的基极电位 第二晶体管稳定，并且防止流过第一差分放大器的工作电流增加。

公开(公告)号：US4902914A

公开(公告)日：1990-02-20

申请号：US154066

申请日：1988-02-09

Applicant: Hideaki Masuoka

Inventor： Hideaki Masuoka

IPC: H01L21/8249 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H03K19/00 ,  H03K19/08 ,  H03K19/0944

CPC classification number: H03K19/0013 ,  H03K19/09448

Abstract: A logic circuit includes first and second NPN bipolar transistors whose collector-emitter paths are serially connected between a power source potential terminal and a ground terminal, the connection node of the first and second bipolar transistors being connected to a signal input terminal; a first CMOS logic circuit having an input terminal connected to a signal input terminal and an output terminal connected to the base of the first NPN bipolar transistor; a second CMOS logic circuit having an input terminal connected to the signal input terminal and an output terminal connected to the signal output terminal; a first switching circuit connected between the signal output terminal and the base of the second bipolar transistor, and to be set OFF when an input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive; and a second switching circuit connected between the second potential supply source and the base of the second NPN bipolar transistor, and to be set OFF when the input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive.

公开(公告)号：US20100265001A1

公开(公告)日：2010-10-21

申请号：US12726474

申请日：2010-03-18

Applicant: Yuki Tsuda ,  Hideaki Masuoka

Inventor： Yuki Tsuda ,  Hideaki Masuoka

IPC: H03L7/099

CPC classification number: H03L7/099 ,  H03L7/087 ,  H03L7/10

Abstract: A digital PLL circuit includes: an oscillation circuit, wherein an oscillation frequency is controlled by changing the number of capacitance elements to be connected in parallel to an inductance element; and a phase comparator part configured to perform a digital phase comparison of a reference clock and a delayed clock thereof, with an oscillation circuit output; and based on the comparison result, to control the number of the capacitance elements so as to bring the phase of the oscillation circuit output closer to the reference clock phase, wherein the capacitance element includes: a coarse adjustment capacitor configured to have a predetermined capacitance; and fine adjustment capacitors configured to have a capacitance of 1/n of that of the coarse adjustment capacitor, wherein a predetermined number of the fine adjustment capacitors function as one coarse adjustment capacitor at the time of coarse adjustment.

Abstract translation: 数字PLL电路包括：振荡电路，其中通过将要并联的电容元件的数量改变为电感元件来控制振荡频率; 以及相位比较器部，被配置为利用振荡电路输出执行基准时钟及其延迟时钟的数字相位比较; 并且基于比较结果，控制电容元件的数量，使振荡电路的输出相位相对于基准时钟相位更接近，其中，电容元件包括：配置为具有预定电容的粗调电容器; 以及微调电容器，其被配置为具有所述粗调电容器的电容的1 / n的电容，其中预定数量的微调电容器在粗调时用作一个粗调电容器。

公开(公告)号：US4906869A

公开(公告)日：1990-03-06

申请号：US201219

申请日：1988-06-02

Applicant: Hideaki Masuoka

Inventor： Hideaki Masuoka

IPC: H01L27/082 ,  H01L21/8222 ,  H03K19/013 ,  H03K19/018 ,  H03K19/086

CPC classification number: H03K19/0136 ,  H03K19/086

Abstract: An output circuit comprising a differential amplifier circuit for providing a pair of complementary output signals corresponding to an input signal supplied to first and second signal input terminals thereof, an output transistor having a base connected to one output node of the differential amplifier circuit, a collector connected to a first power source potential supply terminal, and an emitter connected to a signal output terminal, a current mirror circuit having a current input terminal connected to a current source and a current output terminal connected to the signal output terminal, and a capacitor connected between the other output node of the differential amplifier circuit and the current input terminal of the current mirror circuit.