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1.发明授权Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby 失效制造半导体器件的方法及其制造的半导体器件公开(公告)号：US06383910B2
公开(公告)日：2002-05-07
申请号：US09800579
申请日：2001-03-08
IPC分类号： H01L214763
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.
摘要翻译： 描述了制造半导体器件的方法，其确保对准标记中的台阶的形成，从而提高对准精度。 在包含用于形成对准标记的开口的层间电介质膜上形成钨层。 钨层通过CMP技术磨损。 此时，层间电介质膜的初始厚度大于可识别的对准的最小台阶和磨损量的总和，从而确保对准步骤的形成。 此外，从形成接触对准标记的位置去除栅电极。 或者，从通孔对准标记的正下方的位置除去铝电极。
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公开(公告)号：US20110266657A1
公开(公告)日：2011-11-03
申请号：US13180202
申请日：2011-07-11
IPC分类号： H01L23/02
CPC分类号： H01L23/02 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。
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公开(公告)号：US08829679B2
公开(公告)日：2014-09-09
申请号：US13534844
申请日：2012-06-27
IPC分类号： H01L23/48
CPC分类号： H01L23/02 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。
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公开(公告)号：US20120267793A1
公开(公告)日：2012-10-25
申请号：US13534844
申请日：2012-06-27
IPC分类号： H01L23/498
CPC分类号： H01L23/02 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。
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公开(公告)号：US07998839B2
公开(公告)日：2011-08-16
申请号：US12821703
申请日：2010-06-23
IPC分类号： H01L21/46
CPC分类号： H01L23/02 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。
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公开(公告)号：US07759798B2
公开(公告)日：2010-07-20
申请号：US12426588
申请日：2009-04-20
CPC分类号： H01L23/02 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。
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公开(公告)号：US06602725B2
公开(公告)日：2003-08-05
申请号：US09962199
申请日：2001-09-26
IPC分类号： H01L2166
CPC分类号： H01L21/31053 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
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公开(公告)号：US08232650B2
公开(公告)日：2012-07-31
申请号：US13180202
申请日：2011-07-11
IPC分类号： H01L23/48
CPC分类号： H01L23/02 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.
摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。
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9.发明申请METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE 审中-公开用于制造磁记录装置和磁记忆装置的方法公开(公告)号：US20110121419A1
公开(公告)日：2011-05-26
申请号：US13021079
申请日：2011-02-04
申请人： Shuichi UENO , Haruo Furuta , Ryoji Matsuda , Tatsuya Fukumura , Shin Hasegawa , Shinya Hirano , Hiroyuki Chibahara , Hiroshi Oshita
发明人： Shuichi UENO , Haruo Furuta , Ryoji Matsuda , Tatsuya Fukumura , Shin Hasegawa , Shinya Hirano , Hiroyuki Chibahara , Hiroshi Oshita
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.
摘要翻译： 一种制造包括TMR元件的磁存储器件的方法，所述方法包括：形成下布线层的步骤; 在下布线层上形成层间绝缘层的步骤; 在所述层间绝缘层中形成开口以使所述下部布线层露出的步骤; 形成阻挡金属层以使得层间绝缘层和开口的内表面被覆盖的步骤; 在所述阻挡金属层上形成金属层以使得所述开口嵌入的步骤; 抛光步骤，通过使用阻挡金属层作为阻挡层进行研磨来去除阻挡金属层上的金属层，使得形成包含金属层的布线层嵌入开口和阻挡金属层中; 以及在所述布线层上制造TMR元件的元件制造步骤。
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10.发明授权Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof 失效具有改进的层间导体连接的半导体器件及其制造方法公开(公告)号：US06727170B2
公开(公告)日：2004-04-27
申请号：US09903760
申请日：2001-07-13
IPC分类号： H01L2100
CPC分类号： H01L23/5226 , H01L21/76819 , H01L21/76838 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a first interlayer insulating film smoothly formed on a semiconductor substrate, conductor plugs which are formed by filling openings formed in the first interlayer insulating film so as to be level with the surface of the first interlayer insulating film, a second interlayer insulating film formed on the surface of the first interlayer insulating film and of the conductor plugs, a wiring pattern formed on the second interlayer insulating film, a third interlayer insulating film formed on the surface of the second interlayer insulating film so as to cover the wiring pattern, and an interconnect conductor formed so as to be electrically connected to the conductor plugs by filling the openings penetrating the second and third interlayer insulating films.
摘要翻译： 描述了防止在层间绝缘膜中形成的布线层和形成在布线层附近的垂直导体插塞之间的短路的半导体器件，以及半导体器件的制造方法。 半导体器件包括在半导体衬底上平滑地形成的第一层间绝缘膜，通过填充形成在第一层间绝缘膜中的开口以与第一层间绝缘膜的表面平齐而形成的导体插塞，第二层间绝缘 形成在第一层间绝缘膜和导体插塞的表面上的膜，形成在第二层间绝缘膜上的布线图案，形成在第二层间绝缘膜的表面上以覆盖布线图案的第三层间绝缘膜 以及互连导体，其通过填充贯穿第二和第三层间绝缘膜的开口而形成为与导体插塞电连接。
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