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    Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
    2.
    发明授权
    Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof 失效
    具有改进的层间导体连接的半导体器件及其制造方法

    公开(公告)号：US06278187B1

    公开(公告)日：2001-08-21

    申请号：US09122650

    申请日：1998-07-27

    申请人： Yoshifumi Takata ,  Yuichi Sakai ,  Hiroyuki Chibahara ,  Masanobu Iwasaki

    发明人： Yoshifumi Takata ,  Yuichi Sakai ,  Hiroyuki Chibahara ,  Masanobu Iwasaki

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a first interlayer insulating film smoothly formed on a semiconductor substrate, conductor plugs which are formed by filling openings formed in the first interlayer insulating film so as to be level with the surface of the first interlayer insulating film, a second interlayer insulating film formed on the surface of the first interlayer insulating film and of the conductor plugs, a wiring pattern formed on the second interlayer insulating film, a third interlayer insulating film formed on the surface of the second interlayer insulating film so as to cover the wiring pattern, and an interconnect conductor formed so as to be electrically connected to the conductor plugs by filling the openings penetrating the second and third interlayer insulating films.

    摘要翻译： 描述了防止在层间绝缘膜中形成的布线层和形成在布线层附近的垂直导体插塞之间的短路的半导体器件，以及半导体器件的制造方法。 半导体器件包括在半导体衬底上平滑地形成的第一层间绝缘膜，通过将形成在第一层间绝缘膜中的开口填充以与第一层间绝缘膜的表面平齐而形成的导体插塞，第二层间绝缘膜 形成在第一层间绝缘膜和导体插塞的表面上的膜，形成在第二层间绝缘膜上的布线图案，形成在第二层间绝缘膜的表面上以覆盖布线图案的第三层间绝缘膜 以及互连导体，其通过填充贯穿第二和第三层间绝缘膜的开口而形成为与导体插塞电连接。

    Method of manufacturing interconnection structure of a semiconductor device
    3.
    发明授权
    Method of manufacturing interconnection structure of a semiconductor device 失效
    制造半导体器件的互连结构的方法

    公开(公告)号：US5712140A

    公开(公告)日：1998-01-27

    申请号：US816201

    申请日：1997-03-25

    申请人： Atsushi Ishii ,  Yoshifumi Takata ,  Akihiko Ohsaki ,  Kazuyoshi Maekawa

    发明人： Atsushi Ishii ,  Yoshifumi Takata ,  Akihiko Ohsaki ,  Kazuyoshi Maekawa

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283

    CPC分类号： H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

    摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and a second aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.

    摘要翻译： 铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。 铝互连膜和第二铝互连膜通过形成在氧化硅膜中的通孔电连接。 由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。 因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。 即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。 不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

    Multilayer interconnection structure for a semiconductor device
    4.
    发明授权
    Multilayer interconnection structure for a semiconductor device 失效
    半导体器件的多层互连结构

    公开(公告)号：US5475267A

    公开(公告)日：1995-12-12

    申请号：US354737

    申请日：1994-12-08

    申请人： Atsushi Ishii ,  Yoshifumi Takata ,  Akihiko Ohsaki ,  Kazuyoshi Maekawa

    发明人： Atsushi Ishii ,  Yoshifumi Takata ,  Akihiko Ohsaki ,  Kazuyoshi Maekawa

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/43

    CPC分类号： H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

    摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film, one embodiment using a tungsten plug for the electrical connection. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.

    摘要翻译： 铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。 铝互连膜和铝互连膜通过形成在氧化硅膜中的通孔电连接，一个实施例使用用于电连接的钨塞。 由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。 因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。 即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。 不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

    Method for manufacturing a multilayer wiring structure employing metal fillets at step portions
    5.
    发明授权
    Method for manufacturing a multilayer wiring structure employing metal fillets at step portions 失效
    制造在台阶部分采用金属圆角的多层布线结构的方法

    公开(公告)号：US4962061A

    公开(公告)日：1990-10-09

    申请号：US308622

    申请日：1989-02-10

    申请人： Yoshifumi Takata

    发明人： Yoshifumi Takata

    IPC分类号： H01L21/301 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

    CPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S438/926

    摘要： A method for manufacturing a semiconductor integrated circuit device having a multilayer wiring structure. A semiconductor substrate on which a scribe line portion is to be formed is prepared to form an interlayer insulating film on the semiconductor substrate. Then, the interlayer insulating film at the scribe line portion is etched away so as to expose the scribe line portion on the semiconductor substrate. At this time, a step portion of the interlayer insulating film is formed at the scribe line portion. Then, a metal wiring film is formed on the whole surface of the semiconductor substrate comprising the step portion of this interlayer insulating film and etched away such that the residue of the metal wiring film may be left so as to cover this step portion along the step portion of the interlayer insulating film. By leaving the residue of the metal wiring film thickly and long along the step portion of the interlayer insulating film in this manner, the adhesion between the residue of the metal wiring film and the semiconductor substrate becomes strong and the residue of this metal wiring film is prevented from coming off in the manufacturing steps of a semiconductor integrated circuit device and from contaminating a wafer surface or manufacturing facilities.

    摘要翻译： 一种具有多层布线结构的半导体集成电路器件的制造方法。 准备要在其上形成划线部分的半导体衬底，以在半导体衬底上形成层间绝缘膜。 然后，蚀刻掉划线部分的层间绝缘膜，以露出半导体衬底上的划线部分。 此时，在划线部分形成层间绝缘膜的台阶部分。 然后，在包括该层间绝缘膜的台阶部分的半导体衬底的整个表面上形成金属布线膜，并被蚀刻掉，使得可以留下金属布线膜的残留物以便沿着该步骤覆盖该台阶部分 层间绝缘膜的一部分。 通过以这种方式使金属布线膜的残留物沿着层间绝缘膜的台阶部分厚而长，残留物与半导体基板之间的粘合力变强，并且该金属布线膜的残留物为 防止在半导体集成电路器件的制造步骤中脱落，并且不会污染晶片表面或制造设备。

    Semiconductor device having improved interconnection-wiring structures
    6.
    发明授权
    Semiconductor device having improved interconnection-wiring structures 失效
    具有改进的互连布线结构的半导体器件

    公开(公告)号：US06448658B2

    公开(公告)日：2002-09-10

    申请号：US09757579

    申请日：2001-01-11

    申请人： Yoshifumi Takata ,  Shigeru Harada ,  Hiroki Takewaka

    发明人： Yoshifumi Takata ,  Shigeru Harada ,  Hiroki Takewaka

    IPC分类号： H01L2348

    CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fourth and a fifth interlayer insulating film are formed and a connecting hole which passes through these films is formed. The connecting hole is filled with a metallic plug. The exposed surface of the fifth interlayer insulating film and metallic plug is etched back by dry etching in an atmosphere containing CF4 gas. Thus, the step difference between the surfaces of the metallic plug and fifth interlayer insulating film is reduced. The shape of the connecting hole is shaped so that its opening has a larger diameter at its upper position. The surfaces of the fifth interlayer insulating film and metallic plug are exposed to plasma atmosphere containing oxygen, irradiated with the light having a wavelength of several 10 nm to 400 nm or subjected to the sputter etching using an Ar gas.

    摘要翻译： 形成第四和第五层间绝缘膜，形成穿过这些膜的连接孔。 连接孔填充有金属插头。 第五层间绝缘膜和金属塞的暴露表面在含有CF 4气体的气氛中通过干法蚀刻回蚀刻。 因此，金属插塞和第五层间绝缘膜的表面之间的阶梯差减小。 连接孔的形状成形为使得其开口在其上部位置具有较大的直径。 将第五层间绝缘膜和金属插塞的表面暴露于含有氧的等离子体气氛中，用波长为10nm〜400nm的光照射，或者使用Ar气进行溅射蚀刻。

    Interconnection structure of a semiconductor device
    7.
    发明授权
    Interconnection structure of a semiconductor device 失效
    半导体器件的互连结构

    公开(公告)号：US5442238A

    公开(公告)日：1995-08-15

    申请号：US274379

    申请日：1994-07-13

    申请人： Yoshifumi Takata

    发明人： Yoshifumi Takata

    IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

    CPC分类号： H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

    摘要： A first aluminum interconnection layer includes an aluminum alloy layer 12 and an upper metal layer 13 containing refractory metal. A second aluminum layer 15 is in contact with a surface of upper metal layer 13 through a through-hole 19. A thickness t2 of a contact portion 132 of upper metal layer 13 is smaller than a thickness t1 of a non-contact portion 131. In an interconnection structure for a semiconductor integrated circuit device, the increase in electric resistance by the through-hole is suppressed, and also effects achieved by layer 13 containing refractory metal forming the most upper portion of first aluminum interconnection layer 1A are maintained.

    摘要翻译： 第一铝互连层包括铝合金层12和含有难熔金属的上金属层13。 第二铝层15通过通孔19与上金属层13的表面接触。上金属层13的接触部132的厚度t2小于非接触部131的厚度t1。 在半导体集成电路器件的互连结构中，抑制了通孔的电阻的增加，并且保持了形成第一铝互连层1A的最上部的难熔金属层13所实现的效果。

    Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
    9.
    发明授权
    Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof 失效
    具有改进的层间导体连接的半导体器件及其制造方法

    公开(公告)号：US06727170B2

    公开(公告)日：2004-04-27

    申请号：US09903760

    申请日：2001-07-13

    申请人： Yoshifumi Takata ,  Yuichi Sakai ,  Hiroyuki Chibahara ,  Masanobu Iwasaki

    发明人： Yoshifumi Takata ,  Yuichi Sakai ,  Hiroyuki Chibahara ,  Masanobu Iwasaki

    IPC分类号： H01L2100

    CPC分类号： H01L23/5226 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a first interlayer insulating film smoothly formed on a semiconductor substrate, conductor plugs which are formed by filling openings formed in the first interlayer insulating film so as to be level with the surface of the first interlayer insulating film, a second interlayer insulating film formed on the surface of the first interlayer insulating film and of the conductor plugs, a wiring pattern formed on the second interlayer insulating film, a third interlayer insulating film formed on the surface of the second interlayer insulating film so as to cover the wiring pattern, and an interconnect conductor formed so as to be electrically connected to the conductor plugs by filling the openings penetrating the second and third interlayer insulating films.

    摘要翻译： 描述了防止在层间绝缘膜中形成的布线层和形成在布线层附近的垂直导体插塞之间的短路的半导体器件，以及半导体器件的制造方法。 半导体器件包括在半导体衬底上平滑地形成的第一层间绝缘膜，通过填充形成在第一层间绝缘膜中的开口以与第一层间绝缘膜的表面平齐而形成的导体插塞，第二层间绝缘 形成在第一层间绝缘膜和导体插塞的表面上的膜，形成在第二层间绝缘膜上的布线图案，形成在第二层间绝缘膜的表面上以覆盖布线图案的第三层间绝缘膜 以及互连导体，其通过填充贯穿第二和第三层间绝缘膜的开口而形成为与导体插塞电连接。