公开(公告)号：US08686488B2

公开(公告)日：2014-04-01

申请号：US13602634

申请日：2012-09-04

申请人： Masaki Kondo ,  Nobutoshi Aoki ,  Takashi Izumida ,  Tomomi Yoda

发明人： Masaki Kondo ,  Nobutoshi Aoki ,  Takashi Izumida ,  Tomomi Yoda

IPC分类号： H01L29/788 ,  H01L21/4763

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7883

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的栅绝缘膜，形成在栅极绝缘膜上的浮栅，由含有p型杂质的多晶硅组成， 并且具有层叠在下膜上的下膜和上膜，形成在浮栅上的电极间绝缘膜和形成在电极间绝缘膜上的控制栅电极。 上膜中的p型杂质的浓度和活化浓度之一高于下膜中的p型杂质的浓度和活化浓度之一。

公开(公告)号：US08829623B2

公开(公告)日：2014-09-09

申请号：US12248483

申请日：2008-10-09

申请人： Nobutoshi Aoki ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

发明人： Nobutoshi Aoki ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

IPC分类号： H01L27/088 ,  H01L27/115

CPC分类号： H01L27/11529 ,  H01L27/11524 ,  H01L27/11526

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。

公开(公告)号：US08354706B2

公开(公告)日：2013-01-15

申请号：US12719193

申请日：2010-03-08

申请人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takahisa Kanemura ,  Tomomi Kusaka ,  Takashi Izumida ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

摘要翻译： 根据本发明实施例的半导体存储器件包括衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的第一栅极绝缘体，形成在第一栅绝缘体上的第一浮栅，第二栅绝缘体 形成在第一浮栅上并用作FN隧穿膜的栅极绝缘体，形成在第二栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的栅极绝缘体，以及形成在栅极绝缘体上的控制栅极 所述隔间绝缘体，所述第一和第二浮动栅极中的至少一个包括金属层。

公开(公告)号：US08289782B2

公开(公告)日：2012-10-16

申请号：US12719420

申请日：2010-03-08

申请人： Takashi Izumida ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Tomomi Kusaka ,  Masaki Kondo ,  Nobutoshi Aoki

IPC分类号： G11C16/04

CPC分类号： H01L29/7881 ,  G11C16/0408 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device according to an embodiment of the present invention includes a substrate, a gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the gate insulator, a first intergate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the first intergate insulator, a second intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the second intergate insulator.

摘要翻译： 根据本发明的实施例的半导体存储器件包括：衬底，形成在衬底上并用作FN（Fowler-Nordheim）隧穿膜的栅极绝缘体，形成在栅极绝缘体上的第一浮栅，第一栅极绝缘体 形成在第一浮栅上并用作FN隧道膜，形成在第一栅极绝缘体上的第二浮栅，形成在第二浮栅上并用作电荷阻挡膜的第二栅极绝缘体，以及形成在第一浮栅上的控制栅 第二隔间绝缘子。

公开(公告)号：US20100295112A1

公开(公告)日：2010-11-25

申请号：US12721757

申请日：2010-03-11

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

IPC分类号： H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

摘要翻译： 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

公开(公告)号：US20080246072A1

公开(公告)日：2008-10-09

申请号：US11773721

申请日：2007-07-05

申请人： Masaki Kondo ,  Takashi Izumida ,  Nobutoshi Aoki ,  Toshiharu Watanabe

发明人： Masaki Kondo ,  Takashi Izumida ,  Nobutoshi Aoki ,  Toshiharu Watanabe

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor.

摘要翻译： 在包括存储单元列的非易失性半导体存储器件中，该存储单元列是通过串联连接多个存储单元而形成的，每个存储单元具有通过绝缘层在半导体衬底上层叠电荷存储层和控制栅极的结构，第一选择 形成在半导体衬底上并连接在存储单元列的一端和公共源极线之间的晶体管，以及形成在半导体衬底上并连接在存储单元列的另一端和位线之间的第二选择晶体管， 部分形成在第一选择晶体管和与第一选择晶体管相邻的存储单元之间的半导体衬底的表面上，并且凹陷部分中的第一选择晶体管的一侧的边缘到达第二选择晶体管的一侧的端部 第一选择晶体管的栅极中的存储单元。

公开(公告)号：US08212306B2

公开(公告)日：2012-07-03

申请号：US12721757

申请日：2010-03-11

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

摘要翻译： 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

公开(公告)号：US20100207187A1

公开(公告)日：2010-08-19

申请号：US12644821

申请日：2009-12-22

申请人： Nobutoshi Aoki ,  Masaki Kondo ,  Takashi Izumida

发明人： Nobutoshi Aoki ,  Masaki Kondo ,  Takashi Izumida

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/40114

摘要： A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation.

摘要翻译： 非易失性半导体存储器件包括存储器单元。 存储单元包括形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的浮置栅极，形成在浮置栅极上的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的控制栅极。 浮置栅极包括与第一栅极绝缘膜接触的第一半导体膜和层叠在半导体膜上的金属膜。 在读取操作中，半导体衬底和浮置栅极之间的有效隧道厚度比在半导体衬底和写入操作中浮动之间的有效隧穿厚度厚。

公开(公告)号：US20090101960A1

公开(公告)日：2009-04-23

申请号：US12248483

申请日：2008-10-09

申请人： Nobutoshi AOKI ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

发明人： Nobutoshi AOKI ,  Takashi Izumida ,  Masaki Kondo ,  Fumitaka Arai

IPC分类号： H01L29/788 ,  H01L29/68

CPC分类号： H01L27/11529 ,  H01L27/11524 ,  H01L27/11526

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：接触区域; 选择栅极区; 和存储单元区域; 形成在所述接触区域中并且具有第一深度的第一元件隔离区; 形成在所述选择栅极区中并具有第二深度的第二元件隔离区; 以及形成在所述存储单元区域中并且具有小于所述第一深度的第三深度的第三元件隔离区域。

公开(公告)号：US20110068401A1

公开(公告)日：2011-03-24

申请号：US12881415

申请日：2010-09-14

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Yoshiaki Asao ,  Satoshi Inaba

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Yoshiaki Asao ,  Satoshi Inaba

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/66795

摘要： A semiconductor device of an embodiment includes a substrate and a plurality of fins formed on the substrate. The plurality of fins is arranged so that a first distance and a second distance narrower than the first distance are repeated. In addition, the plurality of fins include a semiconductor region in which an impurity concentration of lower portions of side surfaces facing each other in sides forming the first distance is higher than an impurity concentration of lower portions of side surfaces facing each other in sides forming the second distance.

摘要翻译： 实施例的半导体器件包括基板和形成在基板上的多个翅片。 多个翅片被布置成使得比第一距离窄的第一距离和第二距离被重复。 另外，多个散热片包括半导体区域，其中在形成第一距离的侧面中彼此面对的侧面的下部的杂质浓度高于形成第一距离的侧面彼此相对的侧表面的下部的杂质浓度 第二距离。