公开(公告)号：US4847867A

公开(公告)日：1989-07-11

申请号：US91803

申请日：1987-09-01

申请人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

发明人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4077 ,  G06F13/4256

摘要： A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

摘要翻译： 公开了一种串行数据通信系统。 该系统包括通过单个时钟线和单个数据线互连的多个站。 站中的主站包括用于驱动时钟线的晶体管推挽电路，以在时钟线上输出时钟信号。 因此，时钟信号具有尖锐的引导和下降沿。 数据线耦合到线逻辑装置。 发送站与时钟信号的相关联的时钟脉冲的前沿和下降沿中的一个同步地在数据线上传输数据信号的每一位，并且接收站与另一个的同步接收数据信号的每一位 相关时钟脉冲的前沿和下降沿。

公开(公告)号：US5467461A

公开(公告)日：1995-11-14

申请号：US910780

申请日：1992-07-08

申请人： Masaki Nasu ,  Hajime Sakuma

发明人： Masaki Nasu ,  Hajime Sakuma

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F15/17 ,  G06F15/78 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F15/17 ,  G06F12/0284 ,  G06F12/0692

摘要： A multiprocessor system includes first and second microcomputers, a address decoding mechanism, and a ready signalling device. The address decoder is coupled to an address bus, to decode address information transferred by the second microcomputer, and supplies a request signal to a request signal input terminal of the first microcomputer. A bus control unit of the first microcomputer responds to the request signal to detect whether an internal bus of the first microcomputer is free from being used by the CPU, and outputs an acknowledge signal to an acknowledge signal output terminal when the internal bus is free. The ready signaling device is coupled to the acknowledge signal output terminal to supply the ready signal to a ready signal input terminal of the second microcomputer in response to the acknowledge signal outputted at the acknowledge signal output terminal and the request signal. The bus control unit of the first microcomputer further responds to a strobe signal transferred to a strobe signal input terminal through a strobe signal line from the second microcomputer to access an address of the internal memory by using the address information transferred to a set of first address terminals through the address bus and performs a data read/write operation on the address of the internal memory through the internal bus.

摘要翻译： 多处理器系统包括第一和第二微型计算机，地址解码机制和就绪信号装置。 地址解码器耦合到地址总线，以解码由第二微型计算机传送的地址信息，并将请求信号提供给第一微型计算机的请求信号输入端。 第一微型计算机的总线控制单元响应于请求信号，以检测第一微型计算机的内部总线是否不被CPU使用，并且当内部总线空闲时将确认信号输出到确认信号输出端子。 就绪信号装置耦合到确认信号输出端，以响应于在应答信号输出端输出的应答信号和请求信号，将就绪信号提供给第二微机的就绪信号输入端。 第一微型计算机的总线控制单元还通过来自第二微型计算机的选通信号线响应被传送到选通信号输入端的选通信号，通过使用传送到一组第一地址的地址信息来访问内部存储器的地址 终端通过地址总线，通过内部总线对内部存储器的地址执行数据读/写操作。

公开(公告)号：US5410715A

公开(公告)日：1995-04-25

申请号：US8387

申请日：1993-01-25

申请人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

发明人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.

摘要翻译： 中断控制器包括一个电路，用于保存通过指定从多个中断请求中的每一个的多个优先级中选择的一个优先级获得的信息，以及用于指示是否允许具有至少一个预定的中断请求的中断请求的嵌套的标志 优先考虑多项优先事项。 基于保持在电路中的优先级信息和保持在标志中的信息，控制器操作，使得当在执行具有预定优先级的中断处理的过程中产生中断请求时，如果该标志位于第一 条件是，只有当所产生的中断请求的优先级高于预定优先级时，控制器才确认产生的中断请求，并且如果标志处于第二状态，则控制器不仅在生成的中断请求的优先级 中断请求高于预定优先级，而且当所产生的中断请求的优先级与预定优先级相同时。