公开(公告)号：US20120161139A1

公开(公告)日：2012-06-28

申请号：US13310824

申请日：2011-12-05

申请人： Masami ENDO ,  Kazuaki OHSHIMA

发明人： Masami ENDO ,  Kazuaki OHSHIMA

IPC分类号： H01L29/786 ,  H01L33/16

CPC分类号： H01L27/1225 ,  G09G3/3648 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2320/0214 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/7869

摘要： A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

摘要翻译： 公开了能够控制并保持晶体管的阈值电压达到最佳水平的半导体电路及其驱动方法。 还提供了存储装置，显示装置或包括半导体电路的电子装置。 该半导体电路包括一个二极管和一个设置在一个节点上的第一电容器，待控制的晶体管通过其后门连接到该节点上。 这种结构允许将期望的电压施加到背栅极，使得晶体管的阈值电压被控制在最佳水平并且可以保持很长时间。 可选地提供与二极管并联连接的第二电容器，使得可以暂时改变节点的电压。

公开(公告)号：US20120268164A1

公开(公告)日：2012-10-25

申请号：US13437961

申请日：2012-04-03

申请人： Hidetomo KOBAYASHI ,  Masami ENDO ,  Yutaka SHIONOIRI ,  Hiroki DEMBO ,  Tatsuji NISHIJIMA ,  Kazuaki OHSHIMA ,  Seiichi YONEDA ,  Jun KOYAMA

发明人： Hidetomo KOBAYASHI ,  Masami ENDO ,  Yutaka SHIONOIRI ,  Hiroki DEMBO ,  Tatsuji NISHIJIMA ,  Kazuaki OHSHIMA ,  Seiichi YONEDA ,  Jun KOYAMA

IPC分类号： H03K19/094

CPC分类号： H03K19/17796 ,  G11C16/0433 ,  H01L27/11803 ,  H01L27/1203

摘要： A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.

摘要翻译： 提供了可以执行动态配置的低功耗可编程LSI。 可编程LSI包括多个逻辑元件。 多个逻辑元件各自包括配置存储器。 多个逻辑元件中的每一个执行不同的运算处理，并且根据存储在配置存储器中的配置数据改变逻辑元件之间的电连接。 配置存储器包括一组易失性存储电路和非易失性存储电路。 非易失性存储电路包括其沟道形成在氧化物半导体层中的晶体管和一对电极中的一个电极与晶体管截止时被设置为浮置状态的节点电连接的电容器。

公开(公告)号：US20120292616A1

公开(公告)日：2012-11-22

申请号：US13473014

申请日：2012-05-16

申请人： Kazuaki OHSHIMA

发明人： Kazuaki OHSHIMA

IPC分类号： H01L27/06

CPC分类号： H01L27/105 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/108 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/1776 ,  H03K19/17772

摘要： A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.

摘要翻译： 提供具有新颖结构的半导体器件。 半导体器件包括第一p型晶体管，第二n型晶体管，第三晶体管和第四晶体管。 第三晶体管的源极和漏极之一连接到提供第一电位的布线，另一个连接到第一晶体管的源极和漏极之一。 第二晶体管的源极和漏极之一连接到第一晶体管的源极和漏极中的另一个，另一个连接到第四晶体管的源极和漏极之一。 第四晶体管的源极和漏极中的另一个连接到提供低于第一电位的第二电位的布线。 在第三晶体管和第四晶体管的沟道形成区域中使用氧化物半导体材料。

公开(公告)号：US20060244762A1

公开(公告)日：2006-11-02

申请号：US11279737

申请日：2006-04-13

申请人： Kazuaki OHSHIMA

发明人： Kazuaki OHSHIMA

IPC分类号： G09G5/00

CPC分类号： G06T11/60

摘要： The present invention solves a problem that an operation to input or select an address of an image which is to be synthesized or a name of a part whenever an image included in another folder is synthesized to a screen or an image which is being edited. An image editing method, using a computer including a memory portion and a display portion connected to the computer, includes the steps of reading first image data from the memory portion to display as a first image in an image editing window displayed in the display portion; displaying second image data which is synthesized to the first image as an icon in the image editing window; and displaying the icon as a second image after the icon is selected by an icon selecting means in the image editing window to synthesize the first and second images.

摘要翻译： 本发明解决了当将包含在另一个文件夹中的图像合成到正被编辑的屏幕或图像时，输入或选择要合成的图像的地址的操作或部分的名称的问题。 一种图像编辑方法，使用包括连接到计算机的存储器部分和显示部分的计算机，包括以下步骤：从存储部分读取第一图像数据，以在显示部分中显示的图像编辑窗口中显示为第一图像; 将在第一图像中合成的第二图像数据显示为图像编辑窗口中的图标; 以及在所述图像编辑窗口中的图标选择装置选择所述图标之后，将所述图标显示为第二图像，以合成所述第一和第二图像。

公开(公告)号：US20100072574A1

公开(公告)日：2010-03-25

申请号：US12563608

申请日：2009-09-21

申请人： Kazuaki OHSHIMA

发明人： Kazuaki OHSHIMA

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5228 ,  H01C1/16 ,  H01C13/02 ,  H01L23/5258 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resistor unit is electrically disconnected as necessary. The first resistor units may be either a unit including a single resistor or may be a unit including a plurality of resistors.

摘要翻译： 提供其特性值可以在不需要光刻处理的情况下改变的电阻器。 电阻器包括彼此串联连接的多个第一电阻器单元和与第一电阻器单元的一部分并联连接的第二电阻器单元。 然后，在半导体集成电路的测量之后，根据需要电连接第二电阻器单元。 第一电阻器单元可以是包括单个电阻器的单元，也可以是包括多个电阻器的单元。

公开(公告)号：US20120294060A1

公开(公告)日：2012-11-22

申请号：US13467403

申请日：2012-05-09

申请人： Kazuaki OHSHIMA ,  Hidetomo KOBAYASHI

发明人： Kazuaki OHSHIMA ,  Hidetomo KOBAYASHI

IPC分类号： G11C5/06

CPC分类号： G11C11/005 ,  G11C11/404 ,  G11C14/0009 ,  G11C19/287 ,  H01L27/1225

摘要： A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.

摘要翻译： 提供能够在期望的时刻评估和重写数据的半导体器件。 半导体器件包括寄存器电路，位线和数据线。 寄存器电路包括触发器电路，选择电路和通过选择电路电连接到触发器电路的非易失性存储器电路。 数据线电连接到触发器电路。 位线通过选择电路电连接到非易失性存储器电路。 选择电路基于数据线的电位或非易失性存储器电路中的位线的电位有选择地存储数据。