公开(公告)号：US20070007621A1

公开(公告)日：2007-01-11

申请号：US11390413

申请日：2006-03-28

申请人： Masayoshi Omura ,  Yasuhiko Sekimoto

发明人： Masayoshi Omura ,  Yasuhiko Sekimoto

IPC分类号： H01L29/00 ,  H01L21/82

CPC分类号： H01L27/112 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A plurality of pulses each having relatively low energy are consecutively applied to a subject fuse to cause breakdown, wherein the total energy of pulses is set in light of a prescribed breakdown threshold, which is calculated in advance. The subject fuse has a pair of terminals and an interconnection portion that is narrowly constricted in the middle so as to realize fuse breakdown with ease. A pulse generator generates pulses, which are repeatedly applied to the subject fuse by way of a transistor; then, it stops generating pulses upon detection of fuse breakdown. Side wall spacers are formed on side walls of fuses, which are processed in a tapered shape so as to reduce thermal stress applied to coating insulating films. In addition, pulse energy is appropriately determined so as to cause electro-migration in the subject fuse, which is thus increased in resistance without causing instantaneous meltdown or evaporation.

摘要翻译： 每个具有相对较低能量的多个脉冲被连续地施加到被摄体熔丝以引起击穿，其中根据预先计算的规定的击穿阈值来设置脉冲的总能量。 对象保险丝具有一对端子和在中间狭窄的互连部分，以便容易地实现熔断器击穿。 脉冲发生器产生脉冲，其通过晶体管重复地施加到对象保险丝; 然后，在检测到熔丝故障时，它停止产生脉冲。 侧壁隔板形成在保险丝的侧壁上，其被加工成锥形，以减少施加到涂层绝缘膜上的热应力。 此外，脉冲能量被适当地确定，从而导致对象保险丝中的电迁移，从而电阻增加而不会引起瞬间熔化或蒸发。

公开(公告)号：US20050012159A1

公开(公告)日：2005-01-20

申请号：US10893357

申请日：2004-07-19

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： H01L21/02 ,  H01L21/334 ,  H01L27/06 ,  H01L27/108 ,  H01L29/00 ,  H01L29/76

CPC分类号： H01L27/0629 ,  H01L28/40 ,  H01L29/66181

摘要： A semiconductor device comprises a semiconductor substrate having first and second active regions of first conductivity type, first and second insulated electrodes crossing the first and second active regions, respectively, a third insulated electrode formed on the second insulated electrode, source/drain regions formed on both sides of the first electrode, pseudo source/drain regions formed on both sides of the second electrode, first and second power source lines formed above the second active region through an interlevel insulating layer, a first interconnection connecting the third electrode and the pseudo source/drain regions to the first power source line, and a second interconnection connecting the second electrode to the second power source line, wherein the first active region constitutes a MOS transistor and the second active region constitutes a bypass capacitor and induces an inversion layer of the second conductivity type under the second electrode structure when the power source lines are activated.

摘要翻译： 一种半导体器件包括具有第一和第二有源区的第一导电类型的半导体衬底，分别与第一和第二有源区交叉的第一和第二绝缘电极，形成在第二绝缘电极上的第三绝缘电极，形成在第二绝缘电极上的源/漏区 第一电极的两侧，形成在第二电极的两侧的伪源极/漏极区域，通过层间绝缘层形成在第二有源区域上方的第一和第二电源线，连接第三电极和伪源极的第一互连 /漏极区域连接到第一电源线，以及第二互连件，其将第二电极连接到第二电源线，其中第一有源区域构成MOS晶体管，第二有源区域构成旁路电容器，并且引入第 第二导电类型在第二电极结构下电时 源线被激活。

公开(公告)号：US07239005B2

公开(公告)日：2007-07-03

申请号：US10893357

申请日：2004-07-19

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： H01L29/00

CPC分类号： H01L27/0629 ,  H01L28/40 ,  H01L29/66181

摘要： A semiconductor device comprises a semiconductor substrate having first and second active regions of first conductivity type, first and second insulated electrodes crossing the first and second active regions, respectively, a third insulated electrode formed on the second insulated electrode, source/drain regions formed on both sides of the first electrode, pseudo source/drain regions formed on both sides of the second electrode, first and second power source lines formed above the second active region through an interlevel insulating layer, a first interconnection connecting the third electrode and the pseudo source/drain regions to the first power source line, and a second interconnection connecting the second electrode to the second power source line, wherein the first active region constitutes a MOS transistor and the second active region constitutes a bypass capacitor and induces an inversion layer of the second conductivity type under the second electrode structure when the power source lines are activated.

摘要翻译： 一种半导体器件包括具有第一和第二有源区的第一导电类型的半导体衬底，分别与第一和第二有源区交叉的第一和第二绝缘电极，形成在第二绝缘电极上的第三绝缘电极，形成在第二绝缘电极上的源极/漏极区 第一电极的两侧，形成在第二电极的两侧的伪源极/漏极区域，通过层间绝缘层形成在第二有源区域上方的第一和第二电源线，连接第三电极和伪源极的第一互连 /漏极区域连接到第一电源线，以及第二互连件，其将第二电极连接到第二电源线，其中第一有源区域构成MOS晶体管，第二有源区域构成旁路电容器，并且引入第 第二导电类型在第二电极结构下电时 源线被激活。

公开(公告)号：US06943634B2

公开(公告)日：2005-09-13

申请号：US10396094

申请日：2003-03-25

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： H03K5/19 ,  H03B1/00 ,  H03K3/02 ,  H03K4/02 ,  H03L3/00

CPC分类号： H03K5/19 ,  H03L3/00

摘要： An oscillation detection circuit is constituted by at least one circuitry comprising a first current source for charging a capacitor and a second current source for discharging the capacitor, which are connected in series via a switch controlled to be opened or closed in response to an output signal of an oscillation circuit, wherein the first current source is greater than the second current source in current value. Herein, a signal emerging at a connection point of the first and second current sources is integrated as the switch is repeatedly turned on and off in response to the oscillation signal whose level is periodically changed in an oscillation mode. A Schmitt trigger is arranged to produce a detection signal based on the signal at the connection point between the first and second current sources.

摘要翻译： 振荡检测电路由至少一个电路构成，该电路包括用于对电容器充电的第一电流源和用于对电容器进行放电的第二电流源，该第二电流源通过响应于输出信号而被控制为开或关的开关串联连接 的振荡电路，其中所述第一电流源大于所述第二电流源的电流值。 这里，当第一和第二电流源的连接点出现的信号被集成，因为响应于在振荡模式下电平被周期性地改变的振荡信号，开关被重复接通和断开。 施密特触发器被布置成基于第一和第二电流源之间的连接点处的信号产生检测信号。

公开(公告)号：US5907237A

公开(公告)日：1999-05-25

申请号：US977032

申请日：1997-11-25

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： G05F1/46 ,  G05F2/40

CPC分类号： G05F1/465

摘要： A voltage dropping circuit is formed within an integrated circuit having at least one internal circuit, for dropping an external power supply voltage to generate a dropped voltage, and supplying the dropped voltage to the at least one internal circuit. A voltage divider divides the dropped voltage. A comparator compares the divided voltage with a reference voltage, and generates a control voltage according to a result of the comparison. A voltage generator generates the dropped voltage in response to the control voltage. A setting block sets a ratio of the divided voltage to the dropped voltage.

摘要翻译： 在具有至少一个内部电路的集成电路中形成降压电路，用于降低外部电源电压以产生下降的电压，并将降低的电压提供给至少一个内部电路。 分压器分压掉掉的电压。 比较器将分压与参考电压进行比较，并根据比较结果产生控制电压。 电压发生器响应于控制电压产生下降的电压。 设定块设定分压电压与下降电压的比例。

公开(公告)号：US06903577B2

公开(公告)日：2005-06-07

申请号：US10439492

申请日：2003-05-16

申请人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka ,  Yasuhiko Sekimoto ,  Masamitsu Hirano

发明人： Nobuaki Tsuji ,  Masao Noro ,  Kunihiko Mitsuoka ,  Yasuhiko Sekimoto ,  Masamitsu Hirano

IPC分类号： H03K5/00 ,  H03K5/14 ,  H03K19/0175

CPC分类号： H03K5/13 ,  H03K2005/00156

摘要： An input signal (SIN) is inverted by an inverter (101), and the inverted input signal is entered into a tri-state type inverter (104). An output portion of this inverter is connected via a delay path (105) to an input portion of an operational amplifier (106). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit (103) controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S11) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S16) output from the operational amplifier. As a result, an amplitude of a signal (S15) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (106), and a delay time is made constant.

摘要翻译： 输入信号（SIN）由逆变器（101）反相，反相输入信号进入三态逆变器（104）。 该反相器的输出部分经由延迟路径（105）连接到运算放大器（106）的输入部分。 该运算放大器相对于输入的信号具有滞后特性。 异或门电路（103）控制在接收到通过反相输入信号获得的信号（S11）时将逆变器的输出状态设置为低阻抗状态，并且控制将逆变器的输出状态设置为 在接收到从运算放大器输出的信号（S16）时的高阻抗状态。 结果，响应于运算放大器（106）的滞后特性，信号（S 15）的幅度被限制到恒定幅度，并且延迟时间变得恒定。

公开(公告)号：US06703905B2

公开(公告)日：2004-03-09

申请号：US10253193

申请日：2002-09-24

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： H03B506

CPC分类号： H03K3/0307

摘要： A crystal oscillation circuit using a crystal oscillator comprises an inverting amplifier, a buffer, and a voltage shift circuit. The voltage shift circuit operates in such a way that within prescribed limits by which the output of the inverting amplifier satisfies excitation conditions of the crystal oscillator and by which the oscillation output of the buffer satisfies input conditions of a following circuit, a supply voltage (Vdd) is reduced by a gate threshold voltage of an n-channel MOS transistor, and a ground potential (GND) is increased by a gate threshold voltage of a p-channel MOS transistor with respect to both the inverting amplifier and the buffer. Thus, it is possible to prevent the crystal oscillator from being damaged while suppressing the excitation level of the crystal oscillator even though the gain of the inverting amplifier is increased to be relatively high.

摘要翻译： 使用晶体振荡器的晶体振荡电路包括反相放大器，缓冲器和电压移位电路。 电压移位电路以这样的方式工作，使得在反相放大器的输出满足晶体振荡器的激励条件的规定限度内，缓冲器的振荡输出满足后续电路的输入条件，电源电压（Vdd ）被n沟道MOS晶体管的栅极阈值电压减小，并且接地电位（GND）相对于反相放大器和缓冲器两者都增加了p沟道MOS晶体管的栅极阈值电压。 因此，即使反相放大器的增益增加到相对较高，也可以防止晶体振荡器在抑制晶体振荡器的激励电平的同时被损坏。

公开(公告)号：US07164304B2

公开(公告)日：2007-01-16

申请号：US11293062

申请日：2005-12-02

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： H03K17/16

CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K4/066

摘要： A duty ratio correction circuit includes: a first switching amplifier circuit into which an input pulse signal is input; a current control device connected with the switching device for controlling a current in accordance with a bias voltage signal; a waveform shaping circuit that correct an output of the first switching amplifier circuit; a first integration circuit that integrates a corrected output; a reference voltage setting unit that sets a reference voltage signal defining a duty ratio; a comparator circuit that compares an output of the first integration circuit with the reference voltage signal; a second switching amplifier circuit that includes a switching device connected in series with a constant current circuit, the switching device using a comparison judgment signal as a gate signal; and a second integration circuit that integrates an output of the second switching amplifier circuit and outputs the bias voltage signal.

摘要翻译： 占空比校正电路包括：输入输入脉冲信号的第一开关放大器电路; 与开关装置连接的电流控制装置，用于根据偏置电压信号控制电流; 波形整形电路，其校正第一开关放大器电路的输出; 整合校正输出的第一积分电路; 参考电压设定单元，设定限定占空比的参考电压信号; 比较器电路，其将所述第一积分电路的输出与所述参考电压信号进行比较; 第二开关放大器电路，其包括与恒流电路串联连接的开关器件，所述开关器件使用比较判断信号作为栅极信号; 以及第二积分电路，其对第二开关放大器电路的输出进行积分并输出偏置电压信号。

公开(公告)号：US06975158B2

公开(公告)日：2005-12-13

申请号：US10780158

申请日：2004-02-17

申请人： Yasuhiko Sekimoto

发明人： Yasuhiko Sekimoto

IPC分类号： H03K5/1252 ,  G11C5/00 ,  H03K5/00 ,  H03K5/01 ,  H03K17/16

CPC分类号： H03K5/1252

摘要： A low-pass filter eliminates a high-frequency component contained in an input signal. An inverter outputs a signal at a high level or a low level in response to an output of the low-pass filter that is larger or smaller than a threshold level. A one-shot pulse generating circuit outputs a pulse signal at a point of time when an output level of the inverter is changed. FETs receive the pulse signal output from the one-shot pulse generating circuit, and pulls in forcedly the output of the low-pass filter to the high level or the low level. According to this pulling-in operation, generation of the noise at an output terminal can be prevented.

摘要翻译： 低通滤波器消除了输入信号中包含的高频分量。 反相器响应于大于或小于阈值电平的低通滤波器的输出，反相器输出高电平或低电平的信号。 单脉冲发生电路在逆变器的输出电平变化的时刻输出脉冲信号。 FET接收从单触发脉冲发生电路输出的脉冲信号，并将低通滤波器的输出强制拉至高电平或低电平。 根据该拉入动作，能够防止在输出端产生噪声。

公开(公告)号：US06696891B2

公开(公告)日：2004-02-24

申请号：US10251169

申请日：2002-09-20

申请人： Masao Noro ,  Yasuhiko Sekimoto

发明人： Masao Noro ,  Yasuhiko Sekimoto

IPC分类号： H03F338

CPC分类号： H03F3/2171 ,  H03F2200/331

摘要： A class D amplifier includes: an integrating circuit (1) which integrates an input signal; a flash A/D converter (2) which A/D converts an output signal of the integrating circuit; a waveform converting circuit (3) which produces a PWM signal based on an output of the flash A/D converter; a switching circuit which is includes a pair of MOS transistors (5, 6) connected between a first power source and a second power source, the junction point P of the pair of MOS transistors being connected to a loudspeaker (51); a driving circuit (4) which drives the pair of MOS transistors on the basis of the PWM signal; and a feedback resistor (RNF) which is connected between the junction point P and the input side of the integrating circuit, and negatively feeds back the output signal of the amplifier.

摘要翻译： D类放大器包括：积分电路（1），其对输入信号进行积分; 闪存A / D转换器（2），其对所述积分电路的输出信号进行A / D转换; 波形转换电路（3），其基于闪存A / D转换器的输出产生PWM信号; 开关电路，包括连接在第一电源和第二电源之间的一对MOS晶体管（5,6），所述一对MOS晶体管的接点P连接到扬声器（51）; 驱动电路（4），其基于所述PWM信号驱动所述一对MOS晶体管; 以及连接在积分电路的接合点P和输入侧之间的反馈电阻器（RNF），并且负反馈放大器的输出信号。