公开(公告)号：US06215144B1

公开(公告)日：2001-04-10

申请号：US09236223

申请日：1999-01-25

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L2972

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US06399438B2

公开(公告)日：2002-06-04

申请号：US09828201

申请日：2001-04-09

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L218242

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US06638811B2

公开(公告)日：2003-10-28

申请号：US10157977

申请日：2002-05-31

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L218242

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US06258649B1

公开(公告)日：2001-07-10

申请号：US09389231

申请日：1999-09-03

申请人： Yoshitaka Nakamura ,  Masayoshi Hirasawa ,  Isamu Asano ,  Tsuyoshi Tamaru ,  Satoru Yamada ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Takuya Fukuda

发明人： Yoshitaka Nakamura ,  Masayoshi Hirasawa ,  Isamu Asano ,  Tsuyoshi Tamaru ,  Satoru Yamada ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Takuya Fukuda

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/53223 ,  H01L27/10882 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

摘要翻译： 为了提高连接到DRAM的每个信息存储电容元件的电极的馈电互连的连接可靠性，形成用于连接在每个存储单元选择MISFET上形成的信息存储电容元件的通孔和馈电互连 在与形成用于连接在信息存储电容元件上形成的外围电路中的第二布线层的互连的通孔和形成用于连接对应于第一布线层的互连的通孔中。

公开(公告)号：US20050040452A1

公开(公告)日：2005-02-24

申请号：US10959634

申请日：2004-10-07

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

公开(公告)号：US06492730B1

公开(公告)日：2002-12-10

申请号：US09480480

申请日：2000-01-11

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L2348

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

公开(公告)号：US6028360A

公开(公告)日：2000-02-22

申请号：US106074

申请日：1998-06-29

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L23/48 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

公开(公告)号：US07119443B2

公开(公告)日：2006-10-10

申请号：US10959634

申请日：2004-10-07

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73。 然后，通过溅射法将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，然后，将Ti膜76，Al合金膜75， 并且将TiN膜74图案化以形成第二层布线77和78。

公开(公告)号：US06853081B2

公开(公告)日：2005-02-08

申请号：US10453611

申请日：2003-06-04

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L23/48 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

公开(公告)号：US06605530B2

公开(公告)日：2003-08-12

申请号：US10287616

申请日：2002-11-05

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L214763

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.