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公开(公告)号：US20180247974A1
公开(公告)日：2018-08-30
申请号：US15745914
申请日：2016-07-21
发明人： William D. Oliver , Rabindra N. Das , David J. Hover , Danna Rosenberg , Xhovalin Miloshi , Vladimir Bolkhovsky , Jonilyn L. Yoder , Corey W. Stull , Mark A. Gouker
CPC分类号： H01L27/18 , G06N10/00 , H01L39/045 , H01L39/223 , H01L39/2416 , H01L39/2493 , H01P7/086
摘要： A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called “device”) is provided as a substantially high quality factor, low loss superconducting device.
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公开(公告)号：US20210150402A1
公开(公告)日：2021-05-20
申请号：US17025374
申请日：2020-09-18
发明人： Benjamin Lienhard , William D. Oliver , Simon Gustavsson , Antti Pekka Vepsalainen , Terry Philip Orlando , Luke Colin Gene Govia , Hari Kiran Krovi , Thomas Ohki
摘要： Techniques for machine learning assisted qubit state readout are disclosed. A system a set of training data that describes states of multiple qubits, and trains a neural network to determine qubit states based on the set of training data. The system obtains one or more unlabeled qubit signals, and determines one or more states corresponding to the unlabeled qubit signal(s), using the neural network. The unlabeled qubit signal(s) may include one or more multiplexed qubit signals, and the state(s) corresponding to the unlabeled qubit signal(s) may include one or more multi-qubit states based on the multiplexed qubit signal(s).
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公开(公告)号：US20180013052A1
公开(公告)日：2018-01-11
申请号：US15342589
申请日：2016-11-03
发明人： William D. Oliver , Andrew J. Kerman , Rabindra N. Das , Donna-Ruth W. Yost , Danna Rosenberg , Mark A. Gouker
CPC分类号： H01L39/223 , G06N99/002 , H01L25/0657 , H01L27/18 , H01L39/025 , H01L2224/16225 , H01L2924/15192
摘要： Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).
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公开(公告)号：US11615336B2
公开(公告)日：2023-03-28
申请号：US17188461
申请日：2021-03-01
发明人： William D. Oliver , Simon Gustavsson , Roni Winik , Catherine Leroux , Agustin Di Paolo , Alexandre Blais
摘要： A quantum circuit called a “qumon” is provided to cancel unwanted ZZ interaction in a superconducting qubit architecture. The qumon qubit has a high coherence, and a positive anharmonicity that may be tuned to cancel the negative anharmonicity in a coupled qubit, such as a transmon qubit. The qumon has three parallel branches, in which are a shunt capacitor; a Josephson junction having weighted energy level and capacitance; and several Josephson junctions in series. The weight is chosen to provide the desired anharmonicity, and the transverse flux noise and transverse charge noise each decrease in proportion to the number of the Josephson junctions in series. Because unwanted ZZ interactions are canceled, qumon qubits and transmon qubits may be capacitively coupled in an alternating pattern to provide a surface code in which these interactions are canceled in an extensible way.
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公开(公告)号：US10134972B2
公开(公告)日：2018-11-20
申请号：US15342589
申请日：2016-11-03
发明人： William D. Oliver , Andrew J. Kerman , Rabindra N. Das , Donna-Ruth W. Yost , Danna Rosenberg , Mark A. Gouker
IPC分类号： H01L39/22 , G06N99/00 , H01L39/02 , H01L25/065 , H01L27/18
摘要： A cryogenic quantum bit package with multiple qubit circuits facilitates inter-qubit signal propagation using a multi-chip module (MCM). Multiple qubits are grouped within the package into one or more qubit integrated circuits (ICs). The qubit ICs themselves are electrically coupled to each other via a structure including a superconducting MCM and superconducting interconnects. Coupling of quantum electrical signals between a qubit and other qubits, a substrate, or the MCM uses a coupler circuit, such as a Josephson junction, capacitor, inductor, or resonator.
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6.发明授权公开(公告)号：US11342493B2
公开(公告)日：2022-05-24
申请号：US17106562
申请日：2020-11-30
发明人： William D. Oliver , Simon Gustavsson , I-Jan Wang
摘要： A superconducting qubit is manufactured by stacking up atomically-thin, crystalline monolayers to form a heterostructure held together by van der Waals forces. Two sheets of superconducting material are separated by a third, thin sheet of dielectric to provide both a parallel plate shunting capacitor and a Josephson tunneling barrier. The superconducting material may be a transition metal dichalcogenide (TMD), such as niobium disilicate, and the dielectric may be hexagonal boron nitride. The qubit is etched, or material otherwise removed, to form a magnetic flux loop for tuning. The heterostructure may be protected by adhering additional layers of the dielectric or other insulator on its top and bottom. For readout, the qubit may be coupled to an external resonator, or the resonator may be integral with one of the sheets of superconducting material.
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公开(公告)号：US20210279624A1
公开(公告)日：2021-09-09
申请号：US16809659
申请日：2020-03-05
发明人： William D. Oliver , Youngku Sung , Antti Pekka Vepsalainen , Jochen Braumueller , Simon Gustavsson
IPC分类号： G06N10/00
摘要： According to some embodiments, a method can identify and discriminate contributions from one or more noise sources using the multi-level structure of a quantum system with three or more levels. The method can include: preparing the quantum system in a predetermined state; applying one or more control signals to the quantum system; measuring values of one or more observables of the quantum system that quantify the quantum system's response to the noise sources and the one or more applied control signals; extracting noise spectra information associated with the noise sources from the measured values; and identifying contributions from the one or more noise sources based on the noise spectra information.
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公开(公告)号：US10658424B2
公开(公告)日：2020-05-19
申请号：US15745914
申请日：2016-07-21
发明人： William D. Oliver , Rabindra N. Das , David J. Hover , Danna Rosenberg , Xhovalin Miloshi , Vladimir Bolkhovsky , Jonilyn L. Yoder , Corey W. Stull , Mark A. Gouker
摘要： A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called “device”) is provided as a substantially high quality factor, low loss superconducting device.
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9.发明授权公开(公告)号：US10199553B1
公开(公告)日：2019-02-05
申请号：US15342517
申请日：2016-11-03
发明人： William D. Oliver , Andrew J. Kerman , Rabindra N. Das , Donna-Ruth W. Yost , Danna Rosenberg , Mark A. Gouker
IPC分类号： H01L39/04 , H01L23/498 , H01L23/552
摘要： Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).
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公开(公告)号：US10121754B2
公开(公告)日：2018-11-06
申请号：US15342444
申请日：2016-11-03
发明人： William D. Oliver , Andrew J. Kerman , Rabindra N. Das , Donna-Ruth W. Yost , Danna Rosenberg , Mark A. Gouker
IPC分类号： H01L23/00 , H01L21/02 , H01L21/66 , H01L39/02 , G06N99/00 , H01L25/00 , H01L27/18 , B82Y10/00 , H01L25/065
摘要： A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.
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