公开(公告)号：US07610476B1

公开(公告)日：2009-10-27

申请号：US10729331

申请日：2003-12-05

申请人： Teik-Chung Tan ,  Gregory William Smaus

发明人： Teik-Chung Tan ,  Gregory William Smaus

IPC分类号： G06F9/22 ,  G06F9/30

CPC分类号： G06F9/28 ,  G06F9/30145 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

摘要： Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The microcode ROM may store multiple groups of microcode operations per row. For each group of microcode operations stored in a row, a corresponding control sequence may also be stored in the row. Each group of microcode operations may be included in a microcode routine. The groups of microcode operations stored in a row may be included in the same microcode routine, or some of the groups may be included in different microcode routines.

摘要翻译： 公开了用于存储多组微代码操作和每行微代码ROM的相应控制序列的方法和系统的各种实施例。 在一个实施例中，集成电路可以包括耦合到控制序列逻辑单元的微代码ROM。 微码ROM可以存储每行多组微代码操作。 对于存储在一行中的每组微代码操作，相应的控制序列也可以存储在该行中。 每组微代码操作可以包括在微代码程序中。 存储在一行中的微代码操作组可以包括在相同的微代码例程中，或者一些组可以被包括在不同的微代码例程中。

公开(公告)号：US06760392B1

公开(公告)日：2004-07-06

申请号：US09439191

申请日：1999-11-12

申请人： Teik-Chung Tan ,  Brian D. McMinn

发明人： Teik-Chung Tan ,  Brian D. McMinn

IPC分类号： H04L700

CPC分类号： H04L7/0331 ,  H04L7/02

摘要： A system and method for transferring data using an early response signal to indicate subsequent transmission of data after a fixed latency, wherein the signal and data are transferred from a first clock domain to a second clock domain using a clock skipping technique. In one embodiment, an early response signal is transmitted by a first device k clock pulses prior to transmission of the data. The receiving device, which is operating at a higher clock rate, receives the early response signal and delays the signal by the number of skipped pulses which will occur in the second clock domain before the occurrence of the kth valid pulse. The second device employs a skip pattern generator to generate a signal indicative of this number of skipped pulses and provides the number to a delay circuit which delays the early response signal for an this number of clock pulses. The delayed early response signal is then output to the appropriate logic to indicate the latency of the subsequent data transfer.

摘要翻译： 一种用于使用早期响应信号传送数据以指示固定等待时间之后的数据传输的系统和方法，其中使用时钟跳过技术将信号和数据从第一时钟域传送到第二时钟域。 在一个实施例中，早期响应信号在传输数据之前由第一设备k个时钟脉冲发送。 以较高时钟速率工作的接收设备接收早期响应信号，并且在第k个有效脉冲发生之前将信号延迟将在第二时钟域中发生的跳过脉冲数。 第二设备使用跳过模式发生器来产生指示该跳跃脉冲数的信号，并将数量提供给延迟电路，该延迟电路延迟这个数量的时钟脉冲的早期响应信号。 然后将延迟的早期响应信号输出到适当的逻辑以指示随后的数据传送的等待时间。

公开(公告)号：US09256544B2

公开(公告)日：2016-02-09

申请号：US13726825

申请日：2012-12-26

申请人： Matthew M. Crum ,  Teik-Chung Tan

发明人： Matthew M. Crum ,  Teik-Chung Tan

IPC分类号： G06F12/08 ,  G06F1/32

CPC分类号： G06F12/0895 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

摘要翻译： 对于在处理器处的存储器访问，仅准备存储器与存储器地址相关联的高速缓存的一个子集（少于全部）以进行访问。 基于存储的信息来选择方法的子集，该信息指示对于每个存储器访问，哪个高速缓存的相应方式被访问。 选择方法的子集，并且在最终确定要在子集中访问哪个单独缓存方式之前启动方法子集的准备。

公开(公告)号：US06725337B1

公开(公告)日：2004-04-20

申请号：US09859290

申请日：2001-05-16

申请人： Teik-Chung Tan ,  Benjamin T. Sander

发明人： Teik-Chung Tan ,  Benjamin T. Sander

IPC分类号： G06F1200

CPC分类号： G06F12/0891

摘要： A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

摘要翻译： 配置为推测无效高速缓存行的高速缓存控制器可以立即响应无效请求或指令，而不是等待错误检查完成。 如果错误检查确定无效是错误的，因此不应该执行，则缓存控制器保护推测无效的高速缓存行不被修改，直到错误检查完成。 这样，如果后来发现无效是错误的，则可以颠倒推测无效。 如果错误检查完成而没有检测到任何错误，则推测无效将成为非投机性的。

公开(公告)号：US5870579A

公开(公告)日：1999-02-09

申请号：US751650

申请日：1996-11-18

申请人： Teik-Chung Tan

发明人： Teik-Chung Tan

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3885

摘要： A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. The reorder buffer stores speculatively executed instructions until the instructions prior to the speculatively instruction have completed without exception. When an exception, such as a branch misprediction, occurs, the reorder buffer may cancel the instructions in the reorder buffer after the exception and restore the state of the reorder buffer to the state prior to the execution of the exception. Properly restoring the state of the reorder buffer requires instruction status information about the mispredicted branch instruction, which is stored in the reorder buffer. Additionally, if multiple branch mispredictions are detected, the mispredictions must be prioritized to determine the misprediction that occurred earliest in the program order. To reduce the time delay for identifying mispredicted instructions, prioritizing mispredicted instructions, canceling instructions subsequent to the mispredicted instruction and reading status information from the reorder buffer, the availability of an instruction tag, which identifies the instruction being executed, during the execution of the instruction is utilized. The reorder buffer receives the tag of the instruction issued to the functional unit. In parallel with the execution of the instruction, the reorder buffer generates hit masks identifying instructions to be canceled in the event of a mispredicted branch. In parallel, status information from the instruction (or instructions) being executed is selected from the reorder buffer and prioritization masks are generated. Therefore, if a mispredicted branch is detected, the instructions that need to be canceled can be readily identified and the instruction status information is readily available.

摘要翻译： 超标量微处理器实现重排序缓冲器，以支持指令的无序执行。 重排序缓冲器存储推测性执行的指令，直到推测性指令之前的指令已经完成无一例外。 当发生诸如分支错误预测的异常时，重排序缓冲器可以在异常之后取消重排序缓冲器中的指令，并将重排序缓冲器的状态恢复到执行异常之前的状态。 正确地恢复重排序缓冲器的状态需要关于存储在重排序缓冲器中的错误预测转移指令的指令状态信息。 此外，如果检测到多个分支错误预测，则必须优先考虑错误预测，以确定程序顺序中最早发生的错误预测。 为了减少用于识别误预测指令的时间延迟，对误预测指令进行优先排序，取消误预测指令之后的指令并从重排序缓冲器读取状态信息，在执行指令期间标识正在执行的指令的指令标签的可用性 被利用。 重新排序缓冲器接收发给功能单元的指令标签。 与执行指令并行，重排序缓冲器产生命中掩码，以在错误预测的分支的情况下识别要被取消的指令。 并行地，从重排序缓冲器中选择正在执行的指令（或指令）的状态信息，并生成优先化掩码。 因此，如果检测到错误预测的分支，则可以容易地识别需要取消的指令，并且可以容易地获得指令状态信息。

公开(公告)号：US07464255B1

公开(公告)日：2008-12-09

申请号：US11192153

申请日：2005-07-28

申请人： Teik-Chung Tan ,  Kelvin Domnic Goveas

发明人： Teik-Chung Tan ,  Kelvin Domnic Goveas

IPC分类号： G06F15/00

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30167 ,  G06F9/30181

摘要： A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response to determining a shuffle instruction is received, selected bits of an immediate value of the shuffle instruction are used to generate byte selects for relocating bytes of a source operand. In response to determining the instruction is a shift instruction, the shuffle unit performs an arithmetic operation on a first and second value, where the first value corresponds to a particular destination byte position, and the second value corresponds to the immediate value. The result of the arithmetic operation comprises a byte select which selects one of the bytes of a source operand for conveyance to the particular destination byte position. In the event a destination byte position should be cleared by the shift operation, the output for the particular destination byte position is forced to zero.

摘要翻译： 一种用于使用混洗单元执行移位操作的方法和机构。 处理器包括被配置为响应于随机播放指令执行随机播放操作的洗牌单元。 洗牌单元也适用于支持换档操作。 响应于确定接收到随机播放指令，使用随机播放指令的立即值的选定比特来产生用于重新定位源操作数的字节的字节选择。 响应于确定指令是移位指令，混洗单元对第一和第二值执行算术运算，其中第一值对应于特定目的地字节位置，并且第二值对应于立即值。 算术运算的结果包括字节选择，其选择用于传送到特定目的地字节位置的源操作数的字节之一。 在通过移位操作清除目标字节位置的情况下，特定目的地字节位置的输出被强制为零。

公开(公告)号：US07124236B1

公开(公告)日：2006-10-17

申请号：US10304607

申请日：2002-11-26

申请人： Teik-Chung Tan ,  Mitchell Alsup ,  Jerry D. Moench

发明人： Teik-Chung Tan ,  Mitchell Alsup ,  Jerry D. Moench

IPC分类号： G06F12/00

CPC分类号： G06F12/0853 ,  Y02D10/13

摘要： A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Each of the plurality of storage blocks may be accessed asynchronously. In addition, the cache subsystem includes a plurality of tag units which are coupled to the plurality of storage blocks. Each of the tag units may be configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within the plurality of storage blocks. Each of the plurality of tag units may be accessed synchronously.

摘要翻译： 微处理器包括二级高速缓冲存储器，包括异步可访问的高速缓存块。 微处理器包括耦合到高速缓冲存储器子系统的执行单元，其包括多个存储块，每个存储块被配置为存储多个数据单元。 可以异步地访问多个存储块中的每一个。 另外，缓存子系统包括耦合到多个存储块的多个标签单元。 每个标签单元可以被配置为存储多个标签，每个标签包括对应于存储在多个存储块中的给定的数据单元的地址标签值。 可以同时访问多个标签单元中的每一个。

公开(公告)号：US06571318B1

公开(公告)日：2003-05-27

申请号：US09798469

申请日：2001-03-02

申请人： Benjamin T. Sander ,  William A. Hughes ,  Sridhar P. Subramanian ,  Teik-Chung Tan

发明人： Benjamin T. Sander ,  William A. Hughes ,  Sridhar P. Subramanian ,  Teik-Chung Tan

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A processor is described which includes a stride detect table. The stride detect table includes one or more entries, each entry used to track a potential stride pattern. Additionally, each entry includes a confidence counter. The confidence counter may be incremented each time another address in the pattern is detected, and thus may be indicative of the strength of the pattern (e.g., the likelihood of the pattern repeating). At a first threshold of the confidence counter, prefetching of the next address in the pattern (the most recent address plus the stride) may be initiated. At a second, greater threshold, a more aggressive prefetching may be initiated (e.g. the most recent address plus twice the stride). In some implementations, the prefetch mechanism including the stride detect table may replace a prefetch buffer and prefetch logic in the memory controller.

摘要翻译： 描述了包括步幅检测表的处理器。 步幅检测表包括一个或多个条目，每个条目用于跟踪潜在的步幅图案。 另外，每个条目都包含一个置信计数器。 每次检测到图案中的另一个地址时，置信度计数器可以递增，因此可以指示图案的强度（例如，图案重复的可能性）。 在置信计数器的第一阈值处，可以启动模式中的下一个地址（最近的地址加大步）的预取。 在第二个更大的阈值下，可以启动更积极的预取（例如，最近的地址加上步幅的两倍）。 在一些实现中，包括步幅检测表的预取机制可以替代存储器控制器中的预取缓冲器和预取逻辑。

公开(公告)号：US07584237B1

公开(公告)日：2009-09-01

申请号：US11247628

申请日：2005-10-11

申请人： Teik-Chung Tan ,  Michael Tuuk ,  Wing-Shek Wong

发明人： Teik-Chung Tan ,  Michael Tuuk ,  Wing-Shek Wong

IPC分类号： G06F7/52

CPC分类号： G06F7/49936 ,  G06F7/49926 ,  G06F7/535 ,  G06F7/74

摘要： A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered and the computations required to perform the division. The divisor is normalized by eliminating sign bits. The dividend is prescaled to eliminate one or more sign bits. Prescaling of the dividend may not be precise as sign bits of the dividend may be shifted out as groups of bits, rather than individual bits. Prescaling of the dividend may be adjusted to account for the fact that the divider considers multiple bits of the dividend at a time. Subsequent to prescaling and adjustment, the dividend may be adjusted in dependence upon the normalization of the divisor. Further adjustment may be utilized to maintain a significance relationship between the divisor and dividend. Subsequent to further adjustment, the division operation may be completed.

摘要翻译： 一种执行划分的方法和机制。 处理器包括被配置为执行算术除法运算的分频器。 在除数除数除数之前，除法器可以操纵除数和除数，以减少所考虑的比特数和进行除法所需的计算。 除数通过消除符号位进行归一化。 预先分配股息以消除一个或多个符号位。 股息的预分配可能不是精确的，因为除数的符号位可以作为位组而不是单独位移出。 可以调整股息的预分配以考虑分配器一次考虑股息的多个位的事实。 在预分摊和调整之后，股息可以根据除数的归一化进行调整。 可以采用进一步调整来维持除数与股息之间的重要关系。 在进一步调整之后，分割操作可以完成。

公开(公告)号：US20060195677A1

公开(公告)日：2006-08-31

申请号：US11068548

申请日：2005-02-28

申请人： Teik-Chung Tan

发明人： Teik-Chung Tan

IPC分类号： G06F12/10

CPC分类号： G06F12/1054 ,  G06F12/0846

摘要： A cache system comprises a plurality of cache banks, a translation look-aside buffer (TLB), and a scheduler. The TLB is used to translate a virtual address (VA) to a physical address (PA). The scheduler, before the VA has been completely translated to the PA, uses a subset of the VA's bits to schedule access to the plurality of cache banks.

摘要翻译： 缓存系统包括多个高速缓存组，翻译后备缓冲器（TLB）和调度程序。 TLB用于将虚拟地址（VA）转换为物理地址（PA）。 在VA完全转换到PA之前，调度器使用VA位的子集来调度对多个高速缓冲存储器的访问。