DATA PROCESSING APPARATUS AND METHOD
    3.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD 有权
    数据处理装置和方法

    公开(公告)号:US20090125780A1

    公开(公告)日:2009-05-14

    申请号:US12260327

    申请日:2008-10-29

    IPC分类号: H03M13/00 H04L27/28 G06F11/00

    摘要: A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals. A symbol interleaver is arranged in operation to read-into a symbol interleaver memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals. The set of addresses are generated by an address generator which has been optimised to interleave the data symbols on to the sub-carrier signals of the OFDM carrier signals for a given operating mode of the OFDM system, such as a 32K operating mode for DVB-T2 or DVB-C2.

    摘要翻译: 数据处理装置在正交频分复用(OFDM)符号的预定数量的副载波信号上传送数据位。 数据处理装置包括奇偶校验交织器,其可操作以对通过执行LDPC编码而获得的低密度奇偶校验(LDPC)编码数据比特进行奇偶校验交织,所述LDPC编码数据比特根据LDPC码的奇偶校验矩阵,该LDPC码包括与LDPC码奇偶校验位对应的奇偶校验矩阵 代码,奇偶校验矩阵具有逐步结构,使得LDPC编码数据位的奇偶校验位被交织到不同的奇偶校验位位置。 映射单元将奇偶交织的比特映射到对应于OFDM子载波信号的调制方案的调制符号的数据符号上。 在操作中布置符号交织器以将符号交织器存储器读取用于映射到OFDM子载波信号上的预定数量的数据符号,并且将交织器存储器中的OFDM子载波的数据符号读出到 影响映射,读出的顺序与读入的顺序不同,顺序是从一组地址确定的,其效果是数据符号被交错在子载波信号上。 该地址集由地址发生器产生,该地址发生器已被优化以便在OFDM系统的给定操作模式下将数据符号交织到OFDM载波信号的子载波信号上,诸如用于DVB- T2或DVB-C2。

    2K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard
    5.
    发明授权
    2K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard 有权
    具有奇数交织的2K模式交织器和数字视频广播(DVB)标准中每OFDM符号排列代码变化

    公开(公告)号:US08208525B2

    公开(公告)日:2012-06-26

    申请号:US12257999

    申请日:2008-10-24

    IPC分类号: H03H7/30

    摘要: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

    摘要翻译: 数据处理装置将要传送的输入符号映射到正交频分复用(OFDM)符号的预定数量的副载波信号。 数据处理器包括交织器存储器,其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射,读出的顺序与读入不同,顺序是从一组地址确定的,其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

    8K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard
    6.
    发明授权
    8K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard 有权
    具有奇数交织的8K模式交织器和数字视频广播(DVB)标准中的每个OFDM符号置换码变化

    公开(公告)号:US08199802B2

    公开(公告)日:2012-06-12

    申请号:US12256095

    申请日:2008-10-22

    IPC分类号: H03H7/30

    摘要: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

    摘要翻译: 数据处理装置将要传送的输入符号映射到正交频分复用(OFDM)符号的预定数量的副载波信号。 数据处理器包括交织器存储器,其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射,读出的顺序与读入不同,顺序是从一组地址确定的,其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

    DATA PROCESSING APPARATUS AND METHOD

    公开(公告)号:US20090110094A1

    公开(公告)日:2009-04-30

    申请号:US12256095

    申请日:2008-10-22

    IPC分类号: H04L27/28

    摘要: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R′i[11]=R′i-1[0]R′i-1[1]R′i-1[4]R′i-1[6], and the permutation code forms, with an additional bit, a thirteen bit address. The permutation code is changed from one OFDM symbol to another, thereby providing an improvement in interleaving the data symbols for an 8K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.

    4K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard
    8.
    发明授权
    4K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard 有权
    4K模式交织器,仅在数字视频广播(DVB)标准中仅具有奇数交织和每OFDM符号排列代码变化

    公开(公告)号:US08396104B2

    公开(公告)日:2013-03-12

    申请号:US13398506

    申请日:2012-02-16

    IPC分类号: H03H7/30

    摘要: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R′i[10]=R′i−1[0]⊕R′i−1[2], and the permutation code forms, with an additional bit, a twelve bit address.

    摘要翻译: 数据处理装置将要传送的输入符号映射到正交频分复用(OFDM)符号的预定数量的副载波信号。 数据处理器包括交织器存储器,其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射,读出的顺序与读入不同,顺序是从一组地址确定的,其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。 线性反馈移位寄存器具有11个寄存器级,其中R'i [10] = R'i-1 [0]⊕R'i-1 [2]的线性反馈移位寄存器具有生成多项式,并且置换代码形式 ,附加位,一个十二位地址。

    4K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard
    10.
    发明授权
    4K mode interleaver with odd interleaving only and per OFDM symbol permutation code change in a digital video broadcasting (DVB) standard 有权
    4K模式交织器,仅在数字视频广播(DVB)标准中仅具有奇数交织和每OFDM符号排列代码变化

    公开(公告)号:US08208524B2

    公开(公告)日:2012-06-26

    申请号:US12257010

    申请日:2008-10-23

    IPC分类号: H03H7/30

    摘要: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R′i[10]=R′i-1[0]⊕R′i-1[2], and the permutation code forms, with an additional bit, a twelve bit address.

    摘要翻译: 数据处理装置将要传送的输入符号映射到正交频分复用(OFDM)符号的预定数量的副载波信号。 数据处理器包括交织器存储器,其读入预定数量的数据符号以映射到OFDM子载波信号上。 交织器存储器将数据符号读出到OFDM子载波上以实现映射,读出的顺序与读入不同,顺序是从一组地址确定的,其效果是 数据符号被交织在子载波信号上。 地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。 线性反馈移位寄存器具有11个寄存器级,其中R'i [10] = R'i-1 [0]⊕R'i-1 [2]的线性反馈移位寄存器具有生成多项式,并且置换代码形式 ,附加位,一个十二位地址。