公开(公告)号：US08946821B2

公开(公告)日：2015-02-03

申请号：US13348142

申请日：2012-01-11

申请人： Matthias Goldbach ,  Peter Baars

发明人： Matthias Goldbach ,  Peter Baars

IPC分类号： H01L27/12 ,  H01L27/11 ,  H01L27/02

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

摘要翻译： 提供SRAM集成电路，其具有在硅衬底中及其上制造的SRAM单元的上拉和下拉晶体管。 一层绝缘材料覆盖上拉和下拉晶体管。 SRAM单元的栅极晶体管制造在覆盖绝缘材料层的半导体层中。

公开(公告)号：US20130175627A1

公开(公告)日：2013-07-11

申请号：US13348142

申请日：2012-01-11

申请人： Matthias Goldbach ,  Peter Baars

发明人： Matthias Goldbach ,  Peter Baars

IPC分类号： H01L27/12 ,  H01L21/768

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

摘要翻译： 提供SRAM集成电路，其具有在硅衬底中及其上制造的SRAM单元的上拉和下拉晶体管。 一层绝缘材料覆盖上拉和下拉晶体管。 SRAM单元的栅极晶体管制造在覆盖绝缘材料层的半导体层中。

公开(公告)号：US07374992B2

公开(公告)日：2008-05-20

申请号：US11443602

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

发明人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

公开(公告)号：US20130137234A1

公开(公告)日：2013-05-30

申请号：US13306702

申请日：2011-11-29

申请人： Peter Baars ,  Matthias Goldbach

发明人： Peter Baars ,  Matthias Goldbach

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823821 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66545

摘要： Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.

摘要翻译： 提供了形成半导体器件的方法。 一种方法包括将沟槽蚀刻到硅衬底中并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 形成虚拟门结构，其包括覆盖并横向翅片的第一虚拟栅极结构。 背面填充材料填充在虚拟栅极结构之间。 去除第一伪栅极结构和绝缘材料的上部以暴露鳍片的活动鳍片部分。 主动翅片部分被尺寸修改以形成改变的活动翅片部分。 高k电介质材料和功函数确定栅电极材料沉积在改变的活性鳍片部分上。

公开(公告)号：US20070281416A1

公开(公告)日：2007-12-06

申请号：US11443602

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

发明人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

IPC分类号： H01L21/8244

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

公开(公告)号：US08647938B1

公开(公告)日：2014-02-11

申请号：US13571190

申请日：2012-08-09

申请人： Peter Baars ,  Matthias Goldbach

发明人： Peter Baars ,  Matthias Goldbach

IPC分类号： H01L21/336

CPC分类号： H01L27/1104 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66545

摘要： SRAM ICs and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer. The method involves anisotropically etching U-shaped channels in the oxide layer corresponding to pattern, and thereafter isotropically etching U-shaped channels in the silicon layer to form saddle-shaped fins in the silicon. A second oxide layer is deposited over the saddle-shaped fins, and a first metal layer is deposited over the second oxide layer. A contact metal layer is formed over the first metal layer and planarized to form local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

摘要翻译： 提供SRAM IC及其制造方法。 一种方法包括在覆盖硅衬底的第一氧化物层上沉积光致抗蚀剂，使用所述光致抗蚀剂形成位置图案，以形成两个反相器，每个具有上拉晶体管，下拉晶体管和通过栅极晶体管 所述氧化物层。 该方法涉及各向异性蚀刻对应于图案的氧化物层中的U形通道，然后各向同性蚀刻硅层中的U形通道，以在硅中形成鞍形翅片。 在鞍形翅片上沉积第二氧化物层，并且在第二氧化物层上沉积第一金属层。 接触金属层形成在第一金属层之上并被平坦化以形成将一个反相器的栅电极耦合到另一个反相器的上拉和下拉晶体管之间的节点的局部互连，以及一个通过的一个的源极/漏极 栅极晶体管。

公开(公告)号：US20130193516A1

公开(公告)日：2013-08-01

申请号：US13359242

申请日：2012-01-26

申请人： Matthias Goldbach ,  Peter Baars

发明人： Matthias Goldbach ,  Peter Baars

IPC分类号： H01L27/11 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1104

摘要： SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

摘要翻译： 提供SRAM IC及其制造方法。 一种方法包括形成覆盖在半导体衬底上的虚拟栅电极并且限定用于两个交叉耦合的反相器和两个通过栅极晶体管的栅电极的位置。 第一绝缘层沉积在虚拟栅电极的上方，并且虚设栅电极之间的间隙填充有第二绝缘层。 蚀刻第二绝缘层以形成露出衬底的部分的栅极间开口。 蚀刻第一绝缘层以减小其选定位置的厚度，并且去除伪栅极电极。 栅极电极金属被沉积并平坦化以形成将一个反相器的栅电极耦合到另一个反相器的上拉和下拉晶体管之间的节点的栅电极和局部互连，以及一个通栅晶体管之一的源极/漏极 。

公开(公告)号：US20130099295A1

公开(公告)日：2013-04-25

申请号：US13281236

申请日：2011-10-25

申请人： Peter Baars ,  Matthias Goldbach

发明人： Peter Baars ,  Matthias Goldbach

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

摘要翻译： 提供了半导体器件和相关的制造方法。 示例性的制造方法包括形成一对栅极结构，其具有布置在该对的第一栅极结构和该对的第二栅极结构之间的介质区域，并且在第一栅极结构和第二栅极结构之间的介电区域中形成空隙区域 门结构。 第一和第二栅极结构各自包括第一栅极电极材料，其中该方法通过去除第一栅电极材料继续，以提供对应于栅极结构的第二和第三空隙区域，并在第一空隙区域中形成第二栅电极材料， 第二空隙区域和第三空隙区域。

公开(公告)号：US08735232B2

公开(公告)日：2014-05-27

申请号：US13306702

申请日：2011-11-29

申请人： Peter Baars ,  Matthias Goldbach

发明人： Peter Baars ,  Matthias Goldbach

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L21/823821 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66545

摘要： Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.

摘要翻译： 提供了形成半导体器件的方法。 一种方法包括将沟槽蚀刻到硅衬底中并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 形成虚拟门结构，其包括覆盖并横向翅片的第一虚拟栅极结构。 背面填充材料填充在虚拟栅极结构之间。 去除第一伪栅极结构和绝缘材料的上部以暴露鳍片的活动鳍片部分。 主动翅片部分被尺寸修改以形成改变的活动翅片部分。 高k电介质材料和功函数确定栅电极材料沉积在改变的活性鳍片部分上。

公开(公告)号：US20140042551A1

公开(公告)日：2014-02-13

申请号：US13571190

申请日：2012-08-09

申请人： Peter Baars ,  Matthias Goldbach

发明人： Peter Baars ,  Matthias Goldbach

IPC分类号： H01L21/28 ,  H01L27/088

CPC分类号： H01L27/1104 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66545

摘要： SRAM ICs and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer. The method involves anisotropically etching U-shaped channels in the oxide layer corresponding to pattern, and thereafter isotropically etching U-shaped channels in the silicon layer to form saddle-shaped fins in the silicon. A second oxide layer is deposited over the saddle-shaped fins, and a first metal layer is deposited over the second oxide layer. A contact metal layer is formed over the first metal layer and planarized to form local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

摘要翻译： 提供SRAM IC及其制造方法。 一种方法包括在覆盖硅衬底的第一氧化物层上沉积光致抗蚀剂，使用所述光致抗蚀剂形成位置图案，以形成两个反相器，每个具有上拉晶体管，下拉晶体管和通过栅极晶体管 所述氧化物层。 该方法涉及各向异性蚀刻对应于图案的氧化物层中的U形通道，然后各向同性蚀刻硅层中的U形通道，以在硅中形成鞍形翅片。 在鞍形翅片上沉积第二氧化物层，并且在第二氧化物层上沉积第一金属层。 接触金属层形成在第一金属层之上并被平坦化以形成将一个反相器的栅电极耦合到另一个反相器的上拉和下拉晶体管之间的节点的局部互连，以及一个通过的一个的源极/漏极 栅极晶体管。