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    Manufacturing process of a semiconductor non-volatile memory cell
    1.
    发明授权
    Manufacturing process of a semiconductor non-volatile memory cell 有权
    半导体非易失性存储单元的制造工艺

    公开(公告)号：US07262098B2

    公开(公告)日：2007-08-28

    申请号：US10323615

    申请日：2002-12-18

    申请人： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

    发明人： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

    IPC分类号： H01L29/78

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

    摘要翻译： 一种用于制造具有至少一个栅极区域的非易失性存储单元的工艺，所述方法包括以下步骤：将第一介电层沉积到半导体衬底上; 在所述第一介电层上沉积第一半导体层以形成所述存储单元的浮动栅区; 以及限定第一半导体层中的存储单元的浮置栅极区。 该方法还包括在第一导电层上沉积第二电介质层的步骤，第二电介质层具有比10更高的介电常数。还公开了集成在半导体衬底中并具有栅极区的存储单元，该栅极区具有电介质 层形成在第一导电层上并具有高于10的介电常数。

    Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories
    2.
    发明申请
    Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories 审中-公开

    公开(公告)号：US20060246665A1

    公开(公告)日：2006-11-02

    申请号：US11476361

    申请日：2006-06-27

    申请人： Barbara Crivelli ,  Mauro Alessandri

    发明人： Barbara Crivelli ,  Mauro Alessandri

    IPC分类号： H01L21/336

    CPC分类号： H01L29/511 ,  H01L21/3144 ,  H01L29/40114

    摘要： A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

    Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories
    3.
    发明授权
    Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories 失效

    公开(公告)号：US07084032B2

    公开(公告)日：2006-08-01

    申请号：US10356351

    申请日：2003-01-30

    申请人： Barbara Crivelli ,  Mauro Alessandri

    发明人： Barbara Crivelli ,  Mauro Alessandri

    IPC分类号： H01L21/336

    CPC分类号： H01L29/511 ,  H01L21/28273 ,  H01L21/3144

    摘要： A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

    Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage
    4.
    发明授权
    Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage 有权
    用于制造用于低电压的MOS晶体管，用于高电压的用于低电压，EPROM单元和MOS晶体管的集成电路的工艺

    公开(公告)号：US06319780B2

    公开(公告)日：2001-11-20

    申请号：US09727266

    申请日：2000-11-29

    申请人： Barbara Crivelli ,  Daniela Peschiaroli ,  Elisabetta Palumbo ,  Nicola Zatelli

    发明人： Barbara Crivelli ,  Daniela Peschiaroli ,  Elisabetta Palumbo ,  Nicola Zatelli

    IPC分类号： H01L218234

    CPC分类号： H01L27/11526 ,  H01L27/1052 ,  H01L27/11539 ,  Y10S438/981

    摘要： Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

    摘要翻译： 有源区域和体区形成在用于形成低压MOS晶体管，高压MOS晶体管和EPROM单元的衬底中。 在基板上形成热氧化层，在热氧化层上形成第一多晶硅层。 选择性地去除多晶硅层以形成EPROM单元的浮置栅电极，并且还形成EPROM单元的源极和漏极区。 高电压MOS晶体管的有源区域被暴露，形成一层高温氧化物并氮化。 低电压MOS晶体管的有源区域被暴露，并且在暴露的区域上形成一层热氧化物。 沉积第二多晶硅层，然后选择性地去除以形成低压和高压MOS晶体管的栅电极以及EPROM单元的控制栅电极。