公开(公告)号：US20160322985A1

公开(公告)日：2016-11-03

申请号：US15151042

申请日：2016-05-10

申请人： MaxLinear, Inc.

发明人： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC分类号： H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC分类号： H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

摘要： Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions

摘要翻译： 提供了用于在信号处理期间检测元稳定性的系统和方法。 元稳定性检测器可以包括定时控制电路，多个信号调整电路和多个信号状态电路。 定时控制电路可以测量模数转换期间每个转换周期的比较时间。 每个信号调整电路可以向信号调整电路的一个或多个输入信号施加逻辑运算，并提供对应的输出信号。 至少一个处理周期，每个信号状态电路可以将与一个或多个输入信号有关的状态信息存储到信号状态电路; 并基于先前存储的信息提供输出信号。 多个信号状态电路，多个信号调节电路和定时控制电路可以被布置为在模数转换期间产生用于控制模数转换器（ADC）的一个或多个控制信号

公开(公告)号：US20160006450A1

公开(公告)日：2016-01-07

申请号：US14812327

申请日：2015-07-29

申请人： MaxLinear, Inc.

发明人： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC分类号： H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC分类号： H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

摘要： Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.

摘要翻译： 提供了用于控制信号处理输出的方法和系统。 在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。 调整包括将输出的至少部分设置为预定值。 设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。 可以产生用于控制信号处理电路的输出的产生的定时信息。 定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。

公开(公告)号：US09124291B2

公开(公告)日：2015-09-01

申请号：US13945579

申请日：2013-07-18

申请人： MaxLinear, Inc.

发明人： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC分类号： H03M1/10 ,  H03M1/38 ,  H03M1/12 ,  H03M1/06 ,  H03M1/46

CPC分类号： H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

摘要： A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

摘要翻译： 用于处理信号的系统可以被配置为在数字转换到模拟信号期间检测包括元稳定性事件的特定错误的发生，并且处理任何检测到的元稳定性事件，例如通过调整相应数字的至少一部分 基于元稳定事件检测的输出。 数字输出的调整可以包括至少设置数字输出的一部分，诸如多个预定数字值或模式之一。 系统可以包括用于生成和/或输出预定数字值或码型的码发生器。 系统可以包括选择器，用于针对数字输出的部分，在正常处理路径的输出之间和预定义的值或模式之间自适应地选择。

公开(公告)号：US20180278408A1

公开(公告)日：2018-09-27

申请号：US15991488

申请日：2018-05-29

申请人： MaxLinear, Inc.

发明人： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC分类号： H04L7/033 ,  H03M1/12

CPC分类号： H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

摘要： A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

公开(公告)号：US20180013442A1

公开(公告)日：2018-01-11

申请号：US15711177

申请日：2017-09-21

申请人： Maxlinear, Inc.

发明人： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC分类号： H03M1/06 ,  H03M1/00

CPC分类号： H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

摘要： An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

公开(公告)号：US20170346500A1

公开(公告)日：2017-11-30

申请号：US15674700

申请日：2017-08-11

申请人： MaxLinear, Inc.

发明人： Xuefeng Chen ,  Kok Lim Chan ,  Eric Fogleman ,  Sheng Ye

IPC分类号： H03M1/38 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC分类号： H03M1/38 ,  H03M1/06 ,  H03M1/0682 ,  H03M1/125 ,  H03M1/466

摘要： A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

公开(公告)号：US20140105339A1

公开(公告)日：2014-04-17

申请号：US14107212

申请日：2013-12-16

申请人： MaxLinear, Inc.

发明人： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC分类号： H04L7/033

CPC分类号： H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

摘要： A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.

摘要翻译： 信号接收器可以包括第一采样电路，其可操作以在特定主采样率下以第一电平进行采样; 第二采样电路，其可操作以以与主采样率相比减小的第二采样率在第二电平中采样第一采样电路的输出; 第三采样电路，其可操作以以与第二采样率相比减小的第三采样率在第三电平，第二采样电路的一个或多个输出中采样; 以及用于将模数转换应用于第三采样电路的一个或多个输出的模数转换（ADC）电路。

公开(公告)号：US09985777B2

公开(公告)日：2018-05-29

申请号：US15419063

申请日：2017-01-30

申请人： MaxLinear, Inc.

发明人： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC分类号： H04L7/033 ,  H04B1/10 ,  H03M1/12

CPC分类号： H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

摘要： A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

公开(公告)号：US09559835B2

公开(公告)日：2017-01-31

申请号：US14563476

申请日：2014-12-08

申请人： MaxLinear, Inc.

发明人： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC分类号： H04B1/10 ,  H04L7/033 ,  H03M1/12

CPC分类号： H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

摘要： A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.

摘要翻译： 信号接收机可以包括用于使用包括至少两个不同采样速率的多个采样速率以及用于处理多电平采样的一个或多个输出的电路将多电平采样应用于输入信号的电路。 处理可以包括以与在多级采样期间使用的多个采样率中的每一个不同的采样率进行采样并且应用模数转换。 在处理期间使用的多级采样和/或采样率期间使用的采样率中的至少一个可以基于在多级采样期间和/或处理期间使用的一个或多个时钟信号的配置来设置。 可以基于对应的基本时钟信号的频率的降低来配置一个或多个时钟信号中的至少一个。

公开(公告)号：US09136859B2

公开(公告)日：2015-09-15

申请号：US14585656

申请日：2014-12-30

申请人： MaxLinear, Inc.

发明人： Eric Fogleman ,  Sheng Ye ,  Xuefeng Chen ,  Kok Lim Chan

IPC分类号： H03M1/34 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC分类号： H03M1/0617 ,  H03M1/001 ,  H03M1/069 ,  H03M1/125 ,  H03M1/46 ,  H03M1/462

摘要： An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

摘要翻译： 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中先占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。