公开(公告)号：US20150279799A1

公开(公告)日：2015-10-01

申请号：US14492576

申请日：2014-09-22

申请人： Maxim Integrated Products, Inc.

发明人： Karthik Thambidurai ,  Peter R. Harper ,  Sriram Muthukumar ,  Arkadii V. Samoilov

IPC分类号： H01L23/00 ,  H01L21/78

CPC分类号： H01L24/14 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03474 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/06177 ,  H01L2224/11849 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16106 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11

摘要： A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.

摘要翻译： 描述了晶片级封装，包括晶片级封装的电子器件和制造方法，其包括将悬臂柱设计形成为晶片级封装的一部分和/或用于防止和减少连接应力和增加板级的分段焊接连接 可靠性。 在实现中，采用根据本公开的示例性技术的晶片级器件包括至少一部分经处理的半导体晶片，其包括至少一个集成电路管芯，设置在经处理的半导体晶片上的第一介电层，第一柱， 形成在第一柱上的第二柱，形成在第一介电层上并围绕第一柱和第二柱的一部分的第二介电层，以及设置在第二柱上的至少一个焊球。

公开(公告)号：US10134689B1

公开(公告)日：2018-11-20

申请号：US15280462

申请日：2016-09-29

申请人： Maxim Integrated Products, Inc.

发明人： Vivek S. Sridharan ,  Amit S. Kelkar ,  Sriram Muthukumar

IPC分类号： H01L23/00 ,  H01L21/683 ,  H01L23/58

摘要： A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.

公开(公告)号：US09806047B2

公开(公告)日：2017-10-31

申请号：US14492576

申请日：2014-09-22

申请人： Maxim Integrated Products, Inc.

发明人： Karthik Thambidurai ,  Peter R. Harper ,  Sriram Muthukumar ,  Arkadii V. Samoilov

IPC分类号： H01L23/00 ,  H01L21/78

CPC分类号： H01L24/14 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03474 ,  H01L2224/03903 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/06177 ,  H01L2224/11849 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16106 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11

摘要： A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.