公开(公告)号：US09344208B2

公开(公告)日：2016-05-17

申请号：US13593370

申请日：2012-08-23

申请人： Med Belhadj ,  Hojjat Salemi

发明人： Med Belhadj ,  Hojjat Salemi

IPC分类号： H04J3/06 ,  H04L12/28

CPC分类号： H04J3/0667 ,  H04J3/065 ,  H04J2203/0089

摘要： Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

摘要翻译： 提供了用于为时间和/或频率同步的目的执行定时偏移和/或分数频率偏移的系统和方法。 定时分组在主设备和从设备之间交换。 此外，从设备接收定时调整信息。 从设备使用定时调整信息结合定时分组的发送和接收时间在定时偏移和/或分数频率偏移处进行估计。

公开(公告)号：US08274998B2

公开(公告)日：2012-09-25

申请号：US12285358

申请日：2008-10-02

申请人： Med Belhadj ,  Hojjat Salemi

发明人： Med Belhadj ,  Hojjat Salemi

IPC分类号： H04J3/06

CPC分类号： H04J3/0667 ,  H04J3/065 ,  H04J2203/0089

摘要： Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

摘要翻译： 提供了用于为时间和/或频率同步的目的执行定时偏移和/或分数频率偏移的系统和方法。 定时分组在主设备和从设备之间交换。 此外，从设备接收定时调整信息。 从设备使用定时调整信息结合定时分组的发送和接收时间在定时偏移和/或分数频率偏移处进行估计。

公开(公告)号：US20100085989A1

公开(公告)日：2010-04-08

申请号：US12285358

申请日：2008-10-02

申请人： Med Belhadj ,  Hojjat Salemi

发明人： Med Belhadj ,  Hojjat Salemi

IPC分类号： H04J3/06

CPC分类号： H04J3/0667 ,  H04J3/065 ,  H04J2203/0089

摘要： Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset.

摘要翻译： 提供了用于为时间和/或频率同步的目的执行定时偏移和/或分数频率偏移的系统和方法。 定时分组在主设备和从设备之间交换。 此外，从设备接收定时调整信息。 从设备使用定时调整信息结合定时分组的发送和接收时间在定时偏移和/或分数频率偏移处进行估计。

公开(公告)号：US5917427A

公开(公告)日：1999-06-29

申请号：US879785

申请日：1997-06-20

申请人： Mauricio Peres ,  Hojjat Salemi

发明人： Mauricio Peres ,  Hojjat Salemi

IPC分类号： H04Q11/08 ,  H04Q11/04

CPC分类号： H04Q11/08

摘要： A digital switch array, includes a serial input bus providing a plurality of input streams, each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams, each defining a plurality of time division multiplexed output channels, and an array of digital switches arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device for each output timeslot so that when the enabling device is enabled the associated output timeslot is driven, and at least first and second enabling inputs which when simultaneously activated cause the enabling device to become enabled. An array of activation lines are arranged in rows and columns. The respective rows of activation lines are connected to the first enabling inputs of each row of the digital switches and the respective columns of activation lines are connected to the second enabling inputs of each column of the digital switches. A selected row and column of the activation lines can be simultaneously activated so that the enabling device of the digital switch whose first input is connected to the activated row and whose second input is connected to the activated column becomes enabled.

摘要翻译： 数字开关阵列包括提供多个输入流的串行输入总线，每个输入流定义多个时分多路复用输入通道，提供多个输出流的串行输出总线，每个定义多个时分多路复用输出通道， 以及以行和列排列的数字开关阵列。 每行连接到相应的输入流组，每列连接到相应的输出流组。 数字开关能够在任何输入和任何输出通道之间执行时隙交换。 每个数字开关包括用于每个输出时隙的使能装置，使得当使能装置被使能时，相关联的输出时隙被驱动，并且至少第一和第二使能输入在同时被激活时使得使能装置能够被使能。 激活线阵列以行和列排列。 激活线的相应行被连接到数字开关的每行的第一使能输入，并且各列激活线连接到数字开关的每列的第二使能输入。 可以同时激活所选择的激活线的行和列，使得其第一输入连接到激活的行并且其第二输入连接到激活列的数字开关的使能装置成为可用。

公开(公告)号：US06172626B2

公开(公告)日：2001-01-09

申请号：US09373668

申请日：1999-08-13

申请人： Michael McDonnell ,  Hojjat Salemi

发明人： Michael McDonnell ,  Hojjat Salemi

IPC分类号： H03M740

CPC分类号： H04J3/07 ,  H03M9/00 ,  H04J2203/0089

摘要： A bit stuffing circuit has a first communication channel delivering data to a barrel shifter, the barrel shifter delivering a first number of bits from the first communication channel to a first output. A second output has a predetermined number of bits for transmission, the predetermined number of bits including the first number of bits from the barrel shifter output, and a second number of other bits from a second communications channel.

摘要翻译： 位填充电路具有将数据传送到桶形移位器的第一通信信道，桶形移位器将第一数量的比特从第一通信信道传送到第一输出。 第二输出具有用于传输的预定位数，包括来自桶形移位器输出的第一位数的预定位数和来自第二通信信道的第二数量的其它位。

公开(公告)号：US5999533A

公开(公告)日：1999-12-07

申请号：US880678

申请日：1997-06-23

申请人： Mauricio Peres ,  Hojjat Salemi ,  Michel Laurence

发明人： Mauricio Peres ,  Hojjat Salemi ,  Michel Laurence

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5651 ,  H04L2012/5672 ,  H04L2012/5679

摘要： A method of controlling the supply of cells into an asynchronous network, comprises the steps of storing incoming bytes from multiple channels in respective channel buffers, creating in memory a timing event wheel partitioned into a plurality of sectors, of which one is active at any time, and placing cell pointers in the sectors. The cell pointers identify channel buffers and are distributed around the wheel in accordance with a desired transmission schedule. The wheel is stepwise advanced at a predetermined rate, and the cell pointers in the active sector are scanned at each advance of the wheel to identify the corresponding channel buffers. The bytes from the identified channel buffers are assembled into cells, which are forwarded for transmission over the asynchronous network. These are then multiplexed with VBR cells from another source.

摘要翻译： 一种控制向异步网络提供小区的方法包括以下步骤：将来自多个信道的进入字节存储在相应的信道缓冲器中，在存储器中创建划分成多个扇区的定时事件轮，其中一个在任何时间处于活动状态 ，并将单元格指针放在扇区中。 小区指针识别信道缓冲器并且根据期望的传输调度分布在车轮周围。 轮以预定速率逐步前进，并且在轮的每个前进处扫描活动扇区中的单元指针以识别相应的通道缓冲器。 来自所识别的信道缓冲器的字节被组合成小区，这些小区被转发用于通过异步网络传输。 然后将它们与来自另一来源的VBR细胞复用。

公开(公告)号：US07317733B1

公开(公告)日：2008-01-08

申请号：US10643633

申请日：2003-08-18

申请人： Fredrik Olsson ,  Hojjat Salemi

发明人： Fredrik Olsson ,  Hojjat Salemi

IPC分类号： H04J3/16

CPC分类号： H04J3/047 ,  H04J3/1611 ,  H04J3/1617 ,  H04J3/1623 ,  H04L12/66 ,  H04L69/08 ,  H04L69/12

摘要： A transceiver module includes a protocol converter for converting between the data protocol of a host and a network. In one embodiment the module performs protocol conversion between a TDM data protocol of an external network and a gigabit Ethernet data protocol of host, thereby eliminating the need for additional line cards to perform protocol conversion.

摘要翻译： 收发器模块包括用于在主机的数据协议和网络之间进行转换的协议转换器。 在一个实施例中，该模块在外部网络的TDM数据协议和主机的千兆以太网数据协议之间执行协议转换，从而不需要额外的线路卡来执行协议转换。

公开(公告)号：US5973628A

公开(公告)日：1999-10-26

申请号：US943527

申请日：1997-10-03

申请人： Michael McDonnell ,  Hojjat Salemi

发明人： Michael McDonnell ,  Hojjat Salemi

IPC分类号： H03M9/00 ,  H04J3/07 ,  H04Q11/04 ,  H03M7/40

CPC分类号： H04J3/07 ,  H03M9/00 ,  H04J2203/0089

摘要： A data segmentation circuit is disclosed for use in DS3/STS-1 mapping. The data segmentation circuit uses a circular data buffer to store data for mapping. A recirculating barrel shifter is used for extracting data from within the buffer. A counter moves the barrel shifter window zero, one, five, or eight bits to align the barrel shifter output as necessary to extract a next datum for a next payload envelope location. Data stuffing is then performed. Control circuitry for providing throttling and bit stuffiing as required in an STS-1 information payload is disclosed.

摘要翻译： 公开了一种用于DS3 / STS-1映射的数据分割电路。 数据分割电路使用循环数据缓冲器来存储用于映射的数据。 循环桶形移位器用于从缓冲器内提取数据。 计数器将桶形移位器窗口移动为零，一个，五个或八个位，以根据需要对准桶形移位器输出，以提取下一个有效负载包络位置的下一个数据。 然后执行数据填充。 公开了用于在STS-1信息有效载荷中根据需要提供节流和位填塞的控制电路。

公开(公告)号：US6144674A

公开(公告)日：2000-11-07

申请号：US917101

申请日：1997-08-25

申请人： Mauricio Peres ,  Hojjat Salemi

发明人： Mauricio Peres ,  Hojjat Salemi

IPC分类号： H03L7/14 ,  H04J3/06 ,  H04L12/70 ,  H04L7/04 ,  H04L12/56

CPC分类号： H04J3/0697 ,  H03L7/143 ,  H04J3/0688 ,  H04L2012/5616

摘要： A method of generating timing signals for constant bit rate data received over an asynchronous data network carrying, comprises recovering clock signals from at least two separate sources, selecting one of the sources to drive a phase-locked loop generating a high speed output signal locked to the selected source, dividing the high speed output signal to provide the required timing signals for said constant bit rate data, and continually monitoring the selected source. In the event of failure of the selected source, the phase-locked loop is allowed to free run in a hold-over mode while it is switched over to the other source.

摘要翻译： 一种产生用于通过异步数据网络承载的恒定比特率数据的定时信号的方法，包括从至少两个单独的源恢复时钟信号，选择一个源来驱动锁相环，产生锁定到 所选择的源，分割高速输出信号以为所述恒定比特率数据提供所需的定时信号，并且连续监视所选择的源。 在所选源的故障的情况下，允许锁相环在切换到另一个源时以保持模式自由运行。