-
公开(公告)号：US09148145B2
公开(公告)日：2015-09-29
申请号：US14617865
申请日：2015-02-09
IPC分类号： H03K19/00
CPC分类号： H03K19/0013 , H03K19/0016
摘要： A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal.
摘要翻译： 用于产生相对于时钟输入信号和逻辑使能信号的时钟使能信号的时钟选通电路包括：串联耦合在电源和地之间的第一多个晶体管，用于至少接收逻辑使能信号并产生 第一输出; 串联耦合在电源和地之间的第二多个晶体管，用于至少接收第一输出并产生第二输出; 串联耦合在电源和地之间的第三多个晶体管，用于至少接收第二输出和反相的第二输出; 以及与门电路，用于接收第二输出并产生时钟使能信号。
-
公开(公告)号：US20140292372A1
公开(公告)日：2014-10-02
申请号：US14218998
申请日：2014-03-19
IPC分类号： H03K19/00
CPC分类号： H03K19/0013 , H03K19/0016
摘要： A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.
摘要翻译： 用于产生相对于时钟输入信号和逻辑使能信号的时钟使能信号的时钟选通电路包括：用于至少接收逻辑使能信号并产生第一输出的第一多个晶体管; 第二多个晶体管，用于至少接收所述第一输出并产生第二输出; 用于至少接收第二输出和反相第二输出的第三多个晶体管; 以及与门电路，用于在逻辑使能信号为逻辑1时接收第二输出并产生时钟使能信号。分别在第一多个晶体管，第二多个晶体管和第三多个晶体管中的一个晶体管， 在其门口接收时钟输入信号。
-
公开(公告)号：US20150155870A1
公开(公告)日：2015-06-04
申请号：US14617865
申请日：2015-02-09
IPC分类号： H03K19/00
CPC分类号： H03K19/0013 , H03K19/0016
摘要： A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal.
摘要翻译： 用于产生相对于时钟输入信号和逻辑使能信号的时钟使能信号的时钟选通电路包括：串联耦合在电源和地之间的第一多个晶体管，用于至少接收逻辑使能信号并产生 第一输出; 串联耦合在电源和地之间的第二多个晶体管，用于至少接收第一输出并产生第二输出; 串联耦合在电源和地之间的第三多个晶体管，用于至少接收第二输出和反相的第二输出; 以及与门电路，用于接收第二输出并产生时钟使能信号。
-
公开(公告)号：US10275010B2
公开(公告)日：2019-04-30
申请号：US15119731
申请日：2015-02-16
申请人： MediaTek Singapore Pte. Ltd. , Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32 , G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
-
公开(公告)号：US20170068296A1
公开(公告)日：2017-03-09
申请号：US15119731
申请日：2015-02-16
申请人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist , MediaTek Singapore Pte. Ltd.
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要翻译： 提供了一种检测和防止过电流引起的系统故障的方法。 OC保护控制器根据接收到的CPU活动信息监视CPU总功耗。 响应监视，如果CPU功耗超过阈值，则OC保护控制器输出频率抖动控制信号，以降低CPU时钟频率，使CPU不达到OC限制。 OC保护控制器还输出PLL频率控制信号，以减少PLL时钟频率，提高系统效率。
-
公开(公告)号：US08981815B2
公开(公告)日：2015-03-17
申请号：US14218998
申请日：2014-03-19
IPC分类号： H03K19/00
CPC分类号： H03K19/0013 , H03K19/0016
摘要： A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.
摘要翻译： 用于产生相对于时钟输入信号和逻辑使能信号的时钟使能信号的时钟选通电路包括：用于至少接收逻辑使能信号并产生第一输出的第一多个晶体管; 第二多个晶体管，用于至少接收所述第一输出并产生第二输出; 用于至少接收第二输出和反相第二输出的第三多个晶体管; 以及与门电路，用于在逻辑使能信号为逻辑1时接收第二输出并产生时钟使能信号。分别在第一多个晶体管，第二多个晶体管和第三多个晶体管中的一个晶体管， 在其门口接收时钟输入信号。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.012 秒)
