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    Ultra low area overhead retention flip-flop for power-down applications
    3.
    发明授权
    Ultra low area overhead retention flip-flop for power-down applications 有权
    用于断电应用的超低面积开销保持触发器

    公开(公告)号：US07639056B2

    公开(公告)日：2009-12-29

    申请号：US11138788

    申请日：2005-05-26

    申请人： Sumanth Katte Gururajarao ,  Hugh T. Mair ,  David B. Scott ,  Uming Ko

    发明人： Sumanth Katte Gururajarao ,  Hugh T. Mair ,  David B. Scott ,  Uming Ko

    IPC分类号： H03K3/289 ,  H03K3/356

    CPC分类号： H03K3/356008 ,  H04W52/0283 ,  Y02D70/122

    摘要： In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

    摘要翻译： 在用于数据保持的方法和系统中，数据输入由第一锁存器锁存。 耦合到第一锁存器的第二锁存器接收用于保持的数据输入，而在备用电源模式下第一锁存器不工作。 第一个锁存器在待机电源模式期间从关闭的第一电源线接收电力。 第二锁存器从第二电源线接收电力。 控制器接收时钟输入和保持信号，并向第一锁存器和第二锁存器提供时钟输出。 保持信号的改变表示转变到待机功率模式。 控制器继续将时钟输出保持在预定的电压电平，并且第二锁存器在待机功率模式下继续从第二电源线接收电力，从而保留数据输入。

    Slave latch controlled retention flop with lower leakage and higher performance
    6.
    发明申请
    Slave latch controlled retention flop with lower leakage and higher performance 有权
    从锁存控制保持触发器具有较低的泄漏和更高的性能

    公开(公告)号：US20090058484A1

    公开(公告)日：2009-03-05

    申请号：US11895853

    申请日：2007-08-27

    申请人： Bindu Prabhakar Rao ,  Sumanth Katte Gururajarao ,  Dharin N. Shah

    发明人： Bindu Prabhakar Rao ,  Sumanth Katte Gururajarao ,  Dharin N. Shah

    IPC分类号： H03K3/289

    CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356147

    摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.

    摘要翻译： 在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。 第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。 可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。 切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。 逻辑状态与备用电源模式中保留的数据输入相一致。 备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。

    Ferroelectric latch
    7.
    发明授权
    Ferroelectric latch 有权
    铁电闩

    公开(公告)号：US06947310B1

    公开(公告)日：2005-09-20

    申请号：US10844834

    申请日：2004-05-13

    申请人： Andrew Marshall ,  Sumanth Katte Gururajarao

    发明人： Andrew Marshall ,  Sumanth Katte Gururajarao

    IPC分类号： G11C11/22 ,  G11C14/00

    CPC分类号： G11C14/00 ,  G11C11/22 ,  G11C14/0072

    摘要： Ferroelectric latch type memory devices (102) are provided, comprising an input circuit (110) with first and second internal nodes (N1, N2) coupled with first and second ferroelectric capacitors (CFE1, CFE2), a control circuit (120), a restore circuit (130), and an output circuit (140). The input circuit (110) operates in a first mode to provide the input data state as first and second voltages on the first and second internal nodes (N1, N2), respectively. In a second mode, the input circuit (110) allows the internal nodes (N1, N2) to float, the restore circuit (130) operates to restore the data state from the ferroelectric capacitors (CFE1, CFE2) to the internal nodes (N1, N2), and the output circuit (140) provides a restored data state as an output (OUT).

    摘要翻译： 提供了铁电锁存型存储器件（102），其包括具有与第一和第二铁电电容器（C1H1，...）耦合的第一和第二内部节点（N 1，N 2）的输入电路（110） （FE）2），控制电路（120），恢复电路（130）和输出电路（140）。 输入电路（110）以第一模式操作，以分别在第一和第二内部节点（N1，N2）上提供作为第一和第二电压的输入数据状态。 在第二模式中，输入电路（110）允许内部节点（N 1，N 2）浮动，恢复电路（130）操作以恢复来自强电介质电容器（C SUB FE）的数据状态 > 1，C FE 2）到内部节点（N 1，N 2），并且输出电路（140）提供恢复的数据状态作为输出（OUT）。

    Slave latch controlled retention flop with lower leakage and higher performance
    8.
    发明授权
    Slave latch controlled retention flop with lower leakage and higher performance 有权
    从锁存控制保持触发器具有较低的泄漏和更高的性能

    公开(公告)号：US07652513B2

    公开(公告)日：2010-01-26

    申请号：US11895853

    申请日：2007-08-27

    申请人： Bindu Prabhakar Rao ,  Sumanth Katte Gururajarao ,  Dharin N. Shah

    发明人： Bindu Prabhakar Rao ,  Sumanth Katte Gururajarao ,  Dharin N. Shah

    IPC分类号： H03K3/356

    CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356147

    摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.

    摘要翻译： 在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。 第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。 可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。 切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。 逻辑状态与备用电源模式中保留的数据输入相一致。 备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。

    Low power clock gating circuit
    9.
    发明授权
    Low power clock gating circuit 有权
    低功率时钟门控电路

    公开(公告)号：US09148145B2

    公开(公告)日：2015-09-29

    申请号：US14617865

    申请日：2015-02-09

    申请人： MediaTek Singapore Pte. Ltd.

    发明人： Sumanth Katte Gururajarao

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0013 ,  H03K19/0016

    摘要： A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors coupled in series between a power supply and ground, for receiving at least the logic enable signal and generating a first output; a second plurality of transistor coupled in series between the power supply and ground, for receiving at least the first output and generating a second output; a third plurality of transistors coupled in series between the power supply and ground, for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal.

    摘要翻译： 用于产生相对于时钟输入信号和逻辑使能信号的时钟使能信号的时钟选通电路包括：串联耦合在电源和地之间的第一多个晶体管，用于至少接收逻辑使能信号并产生 第一输出; 串联耦合在电源和地之间的第二多个晶体管，用于至少接收第一输出并产生第二输出; 串联耦合在电源和地之间的第三多个晶体管，用于至少接收第二输出和反相的第二输出; 以及与门电路，用于接收第二输出并产生时钟使能信号。

    LOW POWER CLOCK GATING CIRCUIT
    10.
    发明申请
    LOW POWER CLOCK GATING CIRCUIT 有权
    低功率时钟增益电路

    公开(公告)号：US20140292372A1

    公开(公告)日：2014-10-02

    申请号：US14218998

    申请日：2014-03-19

    申请人： MediaTek Singapore Pte. Ltd.

    发明人： Sumanth Katte Gururajarao

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0013 ,  H03K19/0016

    摘要： A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.

    摘要翻译： 用于产生相对于时钟输入信号和逻辑使能信号的时钟使能信号的时钟选通电路包括：用于至少接收逻辑使能信号并产生第一输出的第一多个晶体管; 第二多个晶体管，用于至少接收所述第一输出并产生第二输出; 用于至少接收第二输出和反相第二输出的第三多个晶体管; 以及与门电路，用于在逻辑使能信号为逻辑1时接收第二输出并产生时钟使能信号。分别在第一多个晶体管，第二多个晶体管和第三多个晶体管中的一个晶体管， 在其门口接收时钟输入信号。