公开(公告)号：US20220353174A1

公开(公告)日：2022-11-03

申请号：US17246736

申请日：2021-05-03

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Barak Gafni ,  Ilya Vershkov

IPC: H04L12/707 ,  H04L12/721

Abstract: A network device includes processing circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The processing circuitry is configured to select a first port among the multiple ports to serve as an egress port for a packet, and to forward the packet to the first port, irrespective of whether or not the first port is usable as the egress port. The processing circuitry is further configured to, when the first port is usable as the egress port, transmit the packet to the communication network via the first port, and when the first port is unusable as the egress port, forward the packet from the first port to a second port among the multiple ports and transmit the packet to the communication network via the second port.

公开(公告)号：US11102146B2

公开(公告)日：2021-08-24

申请号：US16706892

申请日：2019-12-09

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Zachy Haramaty ,  Aviv Kfir ,  Ilya Vershkov ,  Barak Gafni

IPC: H04L12/927 ,  H04L12/46 ,  H04L29/06 ,  H04L29/12 ,  H04L12/911

Abstract: One embodiment includes a network device including multiple interfaces to serve as ingress ports for receiving network packets from nodes in remote customer-site network(s) via a tunnel in a provider network, and from nodes in a local customer-site network, and egress ports for forwarding at least some of the network packets, and control circuitry to make a decision to drop a network packet to reduce packet duplication in at least one of the nodes, responsively to the network packet being identified as a packet of broadcast, unknown unicast, or multicast traffic, the network packet being subject to decapsulation of an encapsulation header, being assigned to one of the egress ports, and having a header including one of a plurality of virtual local area network identifications, or one of a plurality of source identifications.

公开(公告)号：US10944675B1

公开(公告)日：2021-03-09

申请号：US16559658

申请日：2019-09-04

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tom Remen ,  Nir Monovich ,  Gil Levy ,  Aviv Kfir ,  Linor Nehab

IPC: H04L12/743 ,  H04L29/06 ,  H04L12/741

Abstract: A network element includes ports, a hardware fabric, a packet classifier and control logic. The ports are configured to transmit and receive packets over a network. The fabric is configured to forward the packets between the ports. The packet classifier is configured to receive at least some of the packets and to specify an action to be applied to a packet in accordance with a set of rules. The classifier includes (i) multiple Ternary Content Addressable Memories (TCAMs), each TCAM configured to match the packet to a respective subset of the set of rules and to output a match result, and (ii) circuitry configured to specify the action to be applied to the packet based on match results produced for the packet by the multiple TCAMs, and based on a priority defined among the multiple TCAMs. The control logic is configured to apply the specified action to the packet.

公开(公告)号：US20210042251A1

公开(公告)日：2021-02-11

申请号：US16537576

申请日：2019-08-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Lion Levi ,  Aviv Kfir ,  Idan Matari ,  Ran Shani ,  Zachy Haramaty ,  Nir Monovich ,  Matty Kadosh

IPC: G06F13/28 ,  G06F13/40 ,  H04L12/861 ,  H04L12/725

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

公开(公告)号：US20210021503A1

公开(公告)日：2021-01-21

申请号：US16515060

申请日：2019-07-18

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Barak Gafni ,  Zachy Haramaty ,  Gil Levy ,  Liron Mula ,  Jacob Ruthstein ,  Michael Taher

IPC: H04L12/26

Abstract: In one embodiment a network device includes multiple interfaces including at least one egress interface, which is configured to transmit packets belonging to multiple flows to a packet data network, control circuitry configured to generate event-reporting data-items, each including flow and event-type information about a packet-related event occurring in the network device, a memory, and aggregation circuitry configured to aggregate data of at least some of the event-reporting data-items into aggregated-event-reporting data-items aggregated according to the flow and event-type information of the at least some event-reporting data-items, store the aggregated-event-reporting data-items in the memory, and forward one aggregated-event-reporting data-item of the aggregated-event-reporting data-items to a collector node, and purge the one aggregated-event-reporting dam-item from the memory.

公开(公告)号：US20210006513A1

公开(公告)日：2021-01-07

申请号：US16459651

申请日：2019-07-02

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Barak Gafni ,  Aviv Kfir ,  Benny Koren

IPC: H04L12/861 ,  H04L12/863 ,  H04L12/927

Abstract: One embodiment includes a communication apparatus, including multiple interfaces including at least one egress interface to transmit packets belonging to multiple flows to a network, and control circuitry to queue packets belonging to the flows in respective flow-specific queues for transmission via a given egress interface, and to arbitrate among the flow-specific queues so as to select packets for transmission responsively to dynamically changing priorities that are assigned such that all packets in a first flow-specific queue, which is assigned a highest priority among the queues, are transmitted through the given egress interface until the first flow-specific queue is empty, after which the control circuitry assigns the highest priority to a second flow-specific queue, such that all packets in the second flow-specific queue are transmitted through the given egress interface until the second flow-specific queue is empty, after which the control circuitry assigns the highest priority to another flow-specific queue.

公开(公告)号：US10412673B2

公开(公告)日：2019-09-10

申请号：US15607494

申请日：2017-05-28

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Lavi Koch

IPC: G06F1/32 ,  H04W52/02 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3203

Abstract: A network element includes circuitry and multiple ports. The ports are configured to transmit packets to a common destination via multiple paths of a communication network. Each port includes multiple serializers that serially transmit the packets over respective physical lanes. The power consumed by each port is a nonlinear function of the number of serializers activated in the port. The circuitry is configured to select one or more serializers among the ports to (i) meet a throughput demand via the ports and (ii) minimize an overall power consumed by the ports under a constraint of the nonlinear function, and to activate only the selected serializers. The circuitry is configured to choose for a packet received in the network element and destined to the common destination a port in which at least one of the serializers is activated, and to transmit the packet to the common destination via the chosen port.

公开(公告)号：US20190182366A1

公开(公告)日：2019-06-13

申请号：US15836986

申请日：2017-12-11

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Barak Gafni ,  Avner Hadash ,  Ortal Ben Moshe

IPC: H04L29/06

CPC classification number: H04L69/22

Abstract: Communication apparatus includes multiple interfaces configured to be connected to a network so as to receive and transmit data packets having respective packet headers, which can include sub-headers of different, respective types. A memory stores instructions for parsing each type of sub-headers and a transition table, which indicates, for each of the types, a location of the instructions for parsing a subsequent sub-header depending upon the type of the subsequent sub-header. A plurality of predefined types are represented in the transition table by a common alias. Routing logic parses the first sub-header in a packet, reads the type of the second sub-header from the first sub-header, and accesses the transition table using the common alias in place of the type of the first sub-header so as to locate and read the instructions for parsing the second sub-header.

公开(公告)号：US10298500B2

公开(公告)日：2019-05-21

申请号：US15810065

申请日：2017-11-12

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Gil Levy ,  Aviv Kfir

IPC: H04L12/28 ,  H04L12/803 ,  H04L12/743 ,  H04L12/24 ,  H04L12/709 ,  H04L12/707

Abstract: ECMP routing is carried out in fabric of network entities by representing valid destinations and invalid destinations in a group of the entities by a member vector. The order of the elements in the member vector is permuted. A portion of the elements in the permuted vector is pseudo-randomly masked. A flow of packets is transmitted to the first valid destination in the masked member vector.

公开(公告)号：US20190097929A1

公开(公告)日：2019-03-28

申请号：US15713776

申请日：2017-09-25

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Barak Gafni ,  Matty Kadosh ,  Aviv Kfir

IPC: H04L12/743 ,  H04L12/46 ,  H04L12/713 ,  H04L12/741

CPC classification number: H04L45/7453 ,  H04L12/4645 ,  H04L45/54 ,  H04L45/586

Abstract: Communication apparatus includes a plurality of interfaces and routing logic coupled between the interfaces. The routing logic includes a parser, which extracts header data from selected fields of each data packet received from the network through an ingress interface. At least one hash calculator computes a hash over a first set of the header data extracted by the parser from each received data packet. A virtual routing and forwarding (VRF) instance selector selects a VRF instance for each received data packet responsively to both an ingress indicator associated with the received data packet and a second set of the header data extracted by the parser from the received data packet. A lookup engine selects an egress interface responsively to the selected VRF instance and the computed hash. Forwarding and switching logic forwards the data packet to the selected egress interface for transmission to the network.