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公开(公告)号：US20200274733A1
公开(公告)日：2020-08-27
申请号：US16789458
申请日：2020-02-13
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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公开(公告)号：US20180026878A1
公开(公告)日：2018-01-25
申请号：US15218028
申请日：2016-07-24
Inventor： Eitan Zahavi , German Maglione-Mathey , Pedro Yebenes , Jesus Escudero-Sahuquillo , Pedro Javier Garcia , Francisco Jose Quiles
IPC: H04L12/721 , H04L12/733 , H04L12/751 , H04L12/713
CPC classification number: H04L45/38 , H04L45/02 , H04L45/122 , H04L45/586 , H04L45/64 , H04L49/25 , H04L49/258 , H04L49/358
Abstract: A communication apparatus includes an interface and a processor. The interface is configured for connecting to a communication network, including multiple network switches divided into groups. The processor is configured to predefine a strictly monotonic order among the groups, to receive an indication of a flow of packets to be routed from a source endpoint served by a source network switch belonging to a source group to a destination endpoint served by a destination network switch belonging to a destination group, to assign a first Virtual Lane (VL) to the packets in the flow if the destination group succeeds the source group in the predefined order, to assign to the packets in the flow a second VL if the destination group does not succeed the source group in the predefined order, and to configure the network switches to route the packets of the flow in accordance with the assigned VL.
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公开(公告)号：US20170187614A1
公开(公告)日：2017-06-29
申请号：US14979667
申请日：2015-12-28
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Zachy Haramaty , Eitan Zahavi , Itamar Rabenstein
IPC: H04L12/753 , H04L12/44 , H04L12/741 , H04L12/935
CPC classification number: H04L45/48 , H04L12/44 , H04L12/4625 , H04L45/74 , H04L49/3045
Abstract: A switch includes multiple physical ports and forwarding circuitry. The physical ports are configured to receive and send packets over a network. The forwarding circuitry is configured to assign first port numbers to the physical ports, and second port numbers to temporary ports defined in addition to the physical ports, to receive a packet having a destination address via a physical port, to select, based on the destination address, an egress port number for the packet from among the first and second port numbers, to forward the packet to a physical port corresponding to the egress port number if the egress port number is one of the first port numbers, and, if the egress port number is one of the second port numbers, to map a temporary port associated with the egress port number to a mapped physical port and to forward the packet to the mapped physical port.
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公开(公告)号：US12149340B2
公开(公告)日：2024-11-19
申请号：US17413555
申请日：2019-01-03
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Liron Mula , Elad Mentovich , Paraskevas Bakopoulos , Eitan Zahavi , Sagi Kuks
Abstract: A network element (36) includes circuitry and at least one port (72). The at least one port is coupled to an optical fabric (32) including one or more optical switches (40) that provide optical paths between the at least one port and multiple destination nodes, at predefined time slots. The circuitry is configured to hold a schedule plan (84) that specifies which of the destination nodes are accessible via the optical fabric at which of the time slots, to queue packets that are destined to the destination nodes, and to transmit the queued packets via the at least one port in accordance with the schedule plan.
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公开(公告)号：US20220029854A1
公开(公告)日：2022-01-27
申请号：US17495824
申请日：2021-10-07
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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Patent Agency Ranking
公开(公告)号：US10284465B2
公开(公告)日：2019-05-07
申请号：US14979667
申请日：2015-12-28
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Zachy Haramaty , Eitan Zahavi , Itamar Rabenstein
IPC: H04L12/753 , H04L12/46 , H04L12/741 , H04L12/935 , H04L12/44
Abstract: A switch includes multiple physical ports and forwarding circuitry. The physical ports are configured to receive and send packets over a network. The forwarding circuitry is configured to assign first port numbers to the physical ports, and second port numbers to temporary ports defined in addition to the physical ports, to receive a packet having a destination address via a physical port, to select, based on the destination address, an egress port number for the packet from among the first and second port numbers, to forward the packet to a physical port corresponding to the egress port number if the egress port number is one of the first port numbers, and, if the egress port number is one of the second port numbers, to map a temporary port associated with the egress port number to a mapped physical port and to forward the packet to the mapped physical port.
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公开(公告)号：US20180183720A1
公开(公告)日：2018-06-28
申请号：US15387718
申请日：2016-12-22
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Alex Shpiner , Vladimir Zdornov , Zachy Haramaty , Eitan Zahavi
IPC: H04L12/801 , H04L12/707
Abstract: A method for network communication includes receiving in a network element a packet for forwarding to a destination node. The destination node is reachable via two or more candidate ports of the network element that are connected to respective next-hop network elements. Link-level flow-control credit notifications are received in the network element from the next-hop network elements via the respective candidate ports. An egress port is selected for the packet, from among the candidate ports, based at least on the received link-level flow-control credit notifications. The packet is forwarded toward the destination node over the selected egress port.
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8.发明申请公开(公告)号：US20180145900A1
公开(公告)日：2018-05-24
申请号：US15393284
申请日：2016-12-29
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Vladimir Zdornov , Eitan Zahavi
IPC: H04L12/733 , H04L12/947 , H04L12/707
CPC classification number: H04L45/122 , H04L45/06 , H04L45/18 , H04L45/22 , H04L45/24 , H04L45/28 , H04L49/25
Abstract: An apparatus includes a network interface and a processor. The network interface is configured to communicate with a network that includes a plurality of switches interconnected in a Cartesian topology having multiple dimensions. The processor is configured to predefine an order among the dimensions of the Cartesian topology, to search for a preferred route via the network from a source switch to a destination switch, by evaluating candidate routes based at least on respective numbers of switches along the candidate routes for which traversal to a next-hop switch changes from one of the dimensions to another of the dimensions opposite to the predefined order, and to configure one or more of the switches in the network to route packets from the source switch to the destination switch along the preferred route.
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公开(公告)号：US11196586B2
公开(公告)日：2021-12-07
申请号：US16789458
申请日：2020-02-13
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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公开(公告)号：US10404574B2
公开(公告)日：2019-09-03
申请号：US15393284
申请日：2016-12-29
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Vladimir Zdornov , Eitan Zahavi
IPC: H04L12/733 , H04L12/707 , H04L12/947 , H04L12/721 , H04L12/705 , H04L12/703
Abstract: An apparatus includes a network interface and a processor. The network interface is configured to communicate with a network that includes a plurality of switches interconnected in a Cartesian topology having multiple dimensions. The processor is configured to predefine an order among the dimensions of the Cartesian topology, to search for a preferred route via the network from a source switch to a destination switch, by evaluating candidate routes based at least on respective numbers of switches along the candidate routes for which traversal to a next-hop switch changes from one of the dimensions to another of the dimensions opposite to the predefined order, and to configure one or more of the switches in the network to route packets from the source switch to the destination switch along the preferred route.
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