公开(公告)号：US11934568B2

公开(公告)日：2024-03-19

申请号：US17115832

申请日：2020-12-09

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Zachy Haramaty ,  Zvika Eyal ,  Shachar Dor ,  Liron Mula ,  Barry Spinney

IPC: G06F21/85 ,  G06F13/40 ,  G06F21/73 ,  G06F21/86

CPC classification number: G06F21/85 ,  G06F13/4068 ,  G06F21/73 ,  G06F21/86 ,  G06F2221/2103

Abstract: A device including a cable transceiver including cable electrical connections including data electrical connections and control electrical connections, and a hardware memory device, the hardware memory device storing a string identifying a cable and being electrically accessible from externally to the cable transceiver via the control electrical connections. The cable, in electrical connection with the cable electrical connections, may be included in the device. A device for verifying cable authenticity is also described, the device including interface hardware for interfacing a plurality of cables with the device, and verifier circuitry configured to verify that each of the plurality of cables is genuine based on a string stored in a hardware memory device included in each of the plurality of cables. Related apparatus and methods are also described.

公开(公告)号：US11637739B2

公开(公告)日：2023-04-25

申请号：US17145341

申请日：2021-01-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L41/06

Abstract: A network-connected device includes at least one communication port, packet processing circuitry and Diagnostics Direct Memory Access (DMA) Circuitry (DDC). The at least one communication port is configured to communicate packets over a network. The packet processing circuitry is configured to receive, buffer, process and transmit the packets. The DDC is configured to receive a definition of (i) one or more diagnostic events, and (ii) for each diagnostic event, a corresponding list of diagnostic data that is generated in the packet processing circuitry and that pertains to the diagnostic event, and, responsively to occurrence of a diagnostic event, to gather the corresponding list of diagnostic data from the packet processing circuitry.

公开(公告)号：US11558316B2

公开(公告)日：2023-01-17

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L49/90 ,  H04L47/32 ,  H04L49/9047

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

公开(公告)号：US20210182441A1

公开(公告)日：2021-06-17

申请号：US17115832

申请日：2020-12-09

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Zachy Haramaty ,  Zvika Eyal ,  Shachar Dor ,  Liron Mula ,  Barry Spinney

IPC: G06F21/85 ,  G06F21/86 ,  G06F21/73 ,  G06F13/40

Abstract: A device including a cable transceiver including cable electrical connections including data electrical connections and control electrical connections, and a hardware memory device, the hardware memory device storing a string identifying a cable and being electrically accessible from externally to the cable transceiver via the control electrical connections. The cable, in electrical connection with the cable electrical connections, may be included in the device. A device for verifying cable authenticity is also described, the device including interface hardware for interfacing a plurality of cables with the device, and verifier circuitry configured to verify that each of the plurality of cables is genuine based on a string stored in a hardware memory device included in each of the plurality of cables. Related apparatus and methods are also described.

公开(公告)号：US10951549B2

公开(公告)日：2021-03-16

申请号：US16294958

申请日：2019-03-07

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： George Elias ,  Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Benny Koren ,  Sagi Kuks

IPC: H04L12/861 ,  H04L12/935

Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

公开(公告)号：US10182017B2

公开(公告)日：2019-01-15

申请号：US15492003

申请日：2017-04-20

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： David Mozes ,  Liron Mula ,  Benny Koren

IPC: H04L12/875 ,  H04L29/06 ,  H04L12/26

Abstract: A network switch includes circuitry, multiple ports and multiple hardware-implemented distinct-flow counters. The multiple ports are configured to receive packets from a communication network. Each of the multiple hardware-implemented distinct-flow counters is configured to receive (i) a respective count definition specifying one or more packet-header fields and (ii) a respective subset of the received packets, and to estimate a respective number of distinct flows that are present in the subset, by evaluating, over the packets in the subset, a number of distinct values in the packet-header fields belonging to the count definition. The circuitry is configured to provide each of the distinct-flow counters with the respective subset of the received packets, including providing a given packet to a plurality of the distinct-flow counters, and to identify an event-of-interest based on numbers of distinct flows estimated by the distinct-flow counters.

公开(公告)号：US20180241677A1

公开(公告)日：2018-08-23

申请号：US15963118

申请日：2018-04-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Eyal Srebro ,  Sagi Kuks ,  Liron Mula ,  Barak Gafni ,  Benny Koren ,  George Elias ,  Itamar Rabenstein ,  Niv Aibester

IPC: H04L12/801 ,  H04L12/863 ,  H04L12/865 ,  H04L12/851 ,  H04L12/927

CPC classification number: H04L47/12 ,  H04L47/2441 ,  H04L47/6215 ,  H04L47/6255 ,  H04L47/6275 ,  H04L47/6295 ,  H04L47/805

Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.

公开(公告)号：US20210021503A1

公开(公告)日：2021-01-21

申请号：US16515060

申请日：2019-07-18

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Barak Gafni ,  Zachy Haramaty ,  Gil Levy ,  Liron Mula ,  Jacob Ruthstein ,  Michael Taher

IPC: H04L12/26

Abstract: In one embodiment a network device includes multiple interfaces including at least one egress interface, which is configured to transmit packets belonging to multiple flows to a packet data network, control circuitry configured to generate event-reporting data-items, each including flow and event-type information about a packet-related event occurring in the network device, a memory, and aggregation circuitry configured to aggregate data of at least some of the event-reporting data-items into aggregated-event-reporting data-items aggregated according to the flow and event-type information of the at least some event-reporting data-items, store the aggregated-event-reporting data-items in the memory, and forward one aggregated-event-reporting data-item of the aggregated-event-reporting data-items to a collector node, and purge the one aggregated-event-reporting dam-item from the memory.

公开(公告)号：US10412673B2

公开(公告)日：2019-09-10

申请号：US15607494

申请日：2017-05-28

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Lavi Koch

IPC: G06F1/32 ,  H04W52/02 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3203

Abstract: A network element includes circuitry and multiple ports. The ports are configured to transmit packets to a common destination via multiple paths of a communication network. Each port includes multiple serializers that serially transmit the packets over respective physical lanes. The power consumed by each port is a nonlinear function of the number of serializers activated in the port. The circuitry is configured to select one or more serializers among the ports to (i) meet a throughput demand via the ports and (ii) minimize an overall power consumed by the ports under a constraint of the nonlinear function, and to activate only the selected serializers. The circuitry is configured to choose for a packet received in the network element and destined to the common destination a port in which at least one of the serializers is activated, and to transmit the packet to the common destination via the chosen port.

公开(公告)号：US10298500B2

公开(公告)日：2019-05-21

申请号：US15810065

申请日：2017-11-12

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Gil Levy ,  Aviv Kfir

IPC: H04L12/28 ,  H04L12/803 ,  H04L12/743 ,  H04L12/24 ,  H04L12/709 ,  H04L12/707

Abstract: ECMP routing is carried out in fabric of network entities by representing valid destinations and invalid destinations in a group of the entities by a member vector. The order of the elements in the member vector is permuted. A portion of the elements in the permuted vector is pseudo-randomly masked. A flow of packets is transmitted to the first valid destination in the masked member vector.