公开(公告)号：US11425027B2

公开(公告)日：2022-08-23

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L45/00 ,  H04L45/02 ,  H04L45/122 ,  H04L49/00

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

公开(公告)号：US11108679B2

公开(公告)日：2021-08-31

申请号：US16535100

申请日：2019-08-08

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  G06F13/40 ,  H04L12/751 ,  H04L12/707 ,  H04L12/721 ,  H04L12/713

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US20210044513A1

公开(公告)日：2021-02-11

申请号：US16535100

申请日：2019-08-08

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  H04L12/721 ,  H04L12/713 ,  H04L12/751 ,  H04L12/707 ,  G06F13/40

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US11770326B2

公开(公告)日：2023-09-26

申请号：US17368871

申请日：2021-07-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L45/122 ,  G06F13/40 ,  H04L45/02 ,  H04L45/00 ,  H04L45/586

CPC classification number: H04L45/122 ,  G06F13/4036 ,  H04L45/02 ,  H04L45/22 ,  H04L45/38 ,  H04L45/586

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US20220141125A1

公开(公告)日：2022-05-05

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L12/733 ,  H04L12/751 ,  H04L12/721 ,  H04L12/707 ,  H04L12/935

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

公开(公告)号：US20220078104A1

公开(公告)日：2022-03-10

申请号：US17016464

申请日：2020-09-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Vladimir Koushnir ,  Neria Uzan

IPC: H04L12/707 ,  H04L12/44 ,  H04L12/753 ,  H04L12/24

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

公开(公告)号：US11575594B2

公开(公告)日：2023-02-07

申请号：US17016464

申请日：2020-09-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Vladimir Koushnir ,  Neria Uzan

IPC: G06F15/16 ,  H04L45/00 ,  H04L41/12 ,  H04L45/48 ,  H04L12/44

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

公开(公告)号：US20210336868A1

公开(公告)日：2021-10-28

申请号：US17368871

申请日：2021-07-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  G06F13/40 ,  H04L12/751 ,  H04L12/707 ,  H04L12/721 ,  H04L12/713

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.