公开(公告)号：US10938715B2

公开(公告)日：2021-03-02

申请号：US16436945

申请日：2019-06-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Ofir Merdler ,  George Elias ,  Yuval Shpigelman ,  Eyal Srebro ,  Sagi Kuks

IPC: H04L12/773 ,  H04L12/935 ,  H04L12/933 ,  H04L12/861

Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

公开(公告)号：US20210336868A1

公开(公告)日：2021-10-28

申请号：US17368871

申请日：2021-07-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  G06F13/40 ,  H04L12/751 ,  H04L12/707 ,  H04L12/721 ,  H04L12/713

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US11470010B2

公开(公告)日：2022-10-11

申请号：US16783184

申请日：2020-02-06

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Lion Levi ,  Yuval Shpigelman

IPC: H04L47/26 ,  H04L47/10 ,  H04L47/62 ,  H04L47/2425 ,  H04L47/30

Abstract: A network element includes at least one headroom buffer, and flow-control circuitry. The headroom buffer is configured for receiving and storing packets from a peer network element having at least two data sources, each headroom buffer serving multiple packets. The flow-control circuitry is configured to quantify a congestion severity measure, and, in response to detecting a congestion in the headroom buffer, to send to the peer network element pause-request signaling that instructs the peer network element to stop transmitting packets that (i) are associated with the congested headroom buffer and (ii) have priorities that are selected based on the congestion severity measure.

公开(公告)号：US20210250300A1

公开(公告)日：2021-08-12

申请号：US16783184

申请日：2020-02-06

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Lion Levi ,  Yuval Shpigelman

IPC: H04L12/825 ,  H04L12/801 ,  H04L12/835 ,  H04L12/851 ,  H04L12/863

Abstract: A network element includes at least one headroom buffer, and flow-control circuitry. The headroom buffer is configured for receiving and storing packets from a peer network element having at least two data sources, each headroom buffer serving multiple packets. The flow-control circuitry is configured to quantify a congestion severity measure, and, in response to detecting a congestion in the headroom buffer, to send to the peer network element pause-request signaling that instructs the peer network element to stop transmitting packets that (i) are associated with the congested headroom buffer and (ii) have priorities that are selected based on the congestion severity measure.

公开(公告)号：US11108679B2

公开(公告)日：2021-08-31

申请号：US16535100

申请日：2019-08-08

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  G06F13/40 ,  H04L12/751 ,  H04L12/707 ,  H04L12/721 ,  H04L12/713

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US20210044513A1

公开(公告)日：2021-02-11

申请号：US16535100

申请日：2019-08-08

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  H04L12/721 ,  H04L12/713 ,  H04L12/751 ,  H04L12/707 ,  G06F13/40

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US11770326B2

公开(公告)日：2023-09-26

申请号：US17368871

申请日：2021-07-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L45/122 ,  G06F13/40 ,  H04L45/02 ,  H04L45/00 ,  H04L45/586

CPC classification number: H04L45/122 ,  G06F13/4036 ,  H04L45/02 ,  H04L45/22 ,  H04L45/38 ,  H04L45/586

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.