公开(公告)号：US08681528B2

公开(公告)日：2014-03-25

申请号：US13590392

申请日：2012-08-21

申请人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  H01L27/11206

摘要： A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.

摘要翻译： 用于非易失性存储器的一位存储单元包括位线和多个串联存储单元。 位线连接到串行存储单元。 每个存储单元包括形成在基板的表面中的第一掺杂区域，第二掺杂区域和第三掺杂区域。 第一栅极结构设置在第一掺杂区域和第二掺杂区域之间的第一沟道区域上。 第一栅极结构连接到控制信号线。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的第二沟道区域上。 第二栅极结构连接到反熔丝信号线。

公开(公告)号：US20140056051A1

公开(公告)日：2014-02-27

申请号：US13590392

申请日：2012-08-21

申请人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Meng-Yi Wu ,  Yueh-Chia Wen ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/12 ,  G11C17/00

CPC分类号： G11C17/16 ,  H01L27/11206

摘要： A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line.

摘要翻译： 用于非易失性存储器的一位存储器单元包括位线和多个串联存储单元。 位线连接到串行存储单元。 每个存储单元包括形成在基板的表面中的第一掺杂区域，第二掺杂区域和第三掺杂区域。 第一栅极结构设置在第一掺杂区域和第二掺杂区域之间的第一沟道区域上。 第一栅极结构连接到控制信号线。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的第二沟道区域上。 第二栅极结构连接到反熔丝信号线。

公开(公告)号：US20130234228A1

公开(公告)日：2013-09-12

申请号：US13572731

申请日：2012-08-13

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L27/115

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  G11C2216/10 ,  H01L29/42328 ,  H01L29/7883 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮栅晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US20130234227A1

公开(公告)日：2013-09-12

申请号：US13415185

申请日：2012-03-08

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L27/115

CPC分类号： H01L29/42328 ,  G11C16/0408 ,  H01L27/11558 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

公开(公告)号：US20120087170A1

公开(公告)日：2012-04-12

申请号：US12899562

申请日：2010-10-07

申请人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C17/04 ,  G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

摘要翻译： 一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。 一次可编程存储单元阵列包括多个存储单元。 每个存储单元被布置在位线和字线的交点处。 电压泵浦电路包括多个局部升压电路。 每个本地升压电路由多个存储单元的相应存储单元共享。 编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。 每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

公开(公告)号：US08724363B2

公开(公告)日：2014-05-13

申请号：US13413626

申请日：2012-03-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00

CPC分类号： H01L27/11206 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

摘要翻译： 提供具有耦合通道的反熔丝存储器。 反熔丝存储器包括第一导电类型的衬底，第二导电类型的掺杂区域，耦合栅极，栅极介电层，反熔丝栅极和反熔丝层。 衬底具有隔离结构。 掺杂区域设置在衬底中。 在掺杂区域和隔离结构之间限定沟道区域。 耦合栅极设置在掺杂区域和隔离结构之间的衬底上。 耦合栅极与掺杂区域相邻。 栅极电介质层设置在耦合栅极和衬底之间。 反熔丝栅极设置在耦合栅极和隔离结构之间的衬底上。 反熔丝栅极和耦合栅极之间具有间隔。 反熔丝层设置在反熔丝栅极和衬底之间。

公开(公告)号：US08592886B2

公开(公告)日：2013-11-26

申请号：US13572731

申请日：2012-08-13

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L29/788 ,  H01L29/06

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  G11C2216/10 ,  H01L29/42328 ,  H01L29/7883 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮动栅极晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US08456916B2

公开(公告)日：2013-06-04

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US08344445B2

公开(公告)日：2013-01-01

申请号：US13414734

申请日：2012-03-08

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function.

摘要翻译： 具有双重功能的非易失性半导体存储单元包括基板，第一栅极，第二栅极，第三栅极，电荷存储层，第一扩散区域，第二扩散区域和第三扩散区域。 第二栅极和第三栅极用于接收对应于双功能的一次编程功能的第一电压和对应于双功能的多次编程功能的第二电压。 第一扩散区用于接收对应于一次编程功能的第三电压和对应于多次编程功能的第四电压。 第二扩散区用于接收对应于多次编程功能的第五电压。

公开(公告)号：US08339831B2

公开(公告)日：2012-12-25

申请号：US12899562

申请日：2010-10-07

申请人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

摘要翻译： 一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。 一次可编程存储单元阵列包括多个存储单元。 每个存储单元被布置在位线和字线的交点处。 电压泵浦电路包括多个局部升压电路。 每个本地升压电路由多个存储单元的相应存储单元共享。 编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。 每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。