摘要:
An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
摘要:
An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
摘要:
An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要:
An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要:
The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.
摘要:
The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.
摘要:
The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.
摘要:
The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.
摘要:
The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
摘要:
The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.