公开(公告)号：US08724363B2

公开(公告)日：2014-05-13

申请号：US13413626

申请日：2012-03-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00

CPC分类号： H01L27/11206 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

摘要翻译： 提供具有耦合通道的反熔丝存储器。 反熔丝存储器包括第一导电类型的衬底，第二导电类型的掺杂区域，耦合栅极，栅极介电层，反熔丝栅极和反熔丝层。 衬底具有隔离结构。 掺杂区域设置在衬底中。 在掺杂区域和隔离结构之间限定沟道区域。 耦合栅极设置在掺杂区域和隔离结构之间的衬底上。 耦合栅极与掺杂区域相邻。 栅极电介质层设置在耦合栅极和衬底之间。 反熔丝栅极设置在耦合栅极和隔离结构之间的衬底上。 反熔丝栅极和耦合栅极之间具有间隔。 反熔丝层设置在反熔丝栅极和衬底之间。

公开(公告)号：US08456916B2

公开(公告)日：2013-06-04

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US08344445B2

公开(公告)日：2013-01-01

申请号：US13414734

申请日：2012-03-08

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function.

摘要翻译： 具有双重功能的非易失性半导体存储单元包括基板，第一栅极，第二栅极，第三栅极，电荷存储层，第一扩散区域，第二扩散区域和第三扩散区域。 第二栅极和第三栅极用于接收对应于双功能的一次编程功能的第一电压和对应于双功能的多次编程功能的第二电压。 第一扩散区用于接收对应于一次编程功能的第三电压和对应于多次编程功能的第四电压。 第二扩散区用于接收对应于多次编程功能的第五电压。

公开(公告)号：US08339831B2

公开(公告)日：2012-12-25

申请号：US12899562

申请日：2010-10-07

申请人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

摘要翻译： 一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。 一次可编程存储单元阵列包括多个存储单元。 每个存储单元被布置在位线和字线的交点处。 电压泵浦电路包括多个局部升压电路。 每个本地升压电路由多个存储单元的相应存储单元共享。 编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。 每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

公开(公告)号：US20120314474A1

公开(公告)日：2012-12-13

申请号：US13157295

申请日：2011-06-09

申请人： Hsin-Ming Chen ,  Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： G11C17/18 ,  H01L27/12

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/84 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/1203

摘要： The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region.

摘要翻译： 本发明提供一种非易失性存储单元结构。 第一隔离结构设置在衬底上，半导体层设置在第一隔离结构上以形成绝缘体上硅器件。 第一掺杂区域由半导体层的一部分制成。 栅极设置在第一掺杂区域上。 栅极氧化层夹在第一掺杂区域和栅极之间。 第二掺杂区域设置在半导体层内并且在第一掺杂区域的外部。 第二掺杂区域与第一掺杂区域直接接触。 第二隔离结构设置在第一隔离结构上。 此外，第二隔离结构围绕第一掺杂区域和第二掺杂区域。 第二隔离结构也与第一掺杂区和第二掺杂区直接接触。

公开(公告)号：US08174063B2

公开(公告)日：2012-05-08

申请号：US12633780

申请日：2009-12-08

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其之间形成自对准电荷存储层的距离。

公开(公告)号：US20120007161A1

公开(公告)日：2012-01-12

申请号：US13237976

申请日：2011-09-21

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

摘要： A method of forming a charge-storing layer in a non-volatile memory cell in a logic process includes forming a select gate over an active region of a substrate, forming long polysilicon gates partially overlapping the active region of the substrate, and filling the charge-storing layer between the long polysilicon gates.

摘要翻译： 在逻辑处理中在非易失性存储单元中形成电荷存储层的方法包括：在衬底的有源区上形成选择栅极，形成与衬底的有源区域部分重叠的长多晶硅栅极，并填充电荷 在多晶硅多栅极之间的层间。

公开(公告)号：US20120087170A1

公开(公告)日：2012-04-12

申请号：US12899562

申请日：2010-10-07

申请人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C17/04 ,  G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

摘要翻译： 一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。 一次可编程存储单元阵列包括多个存储单元。 每个存储单元被布置在位线和字线的交点处。 电压泵浦电路包括多个局部升压电路。 每个本地升压电路由多个存储单元的相应存储单元共享。 编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。 每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

公开(公告)号：US08072401B2

公开(公告)日：2011-12-06

申请号：US11689900

申请日：2007-03-22

申请人： Hau-yan Lu ,  Chi-wen Chen ,  Ting-chang Chang

发明人： Hau-yan Lu ,  Chi-wen Chen ,  Ting-chang Chang

IPC分类号： G09G3/32

CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/043

摘要： A pixel circuit includes a first transistor coupled to a supply voltage end, a second transistor coupled to a ground end, a storage capacitor, a third transistor coupled to a data end, a fourth transistor, a fifth transistor coupled to the second transistor and the second end of the storage capacitor, and a light-emitting element coupled to the fourth transistor. The first transistor is used for conducting a supply voltage from the supply voltage end in response to a trigger of an enable signal. The second transistor is used for conducting a ground voltage from the ground end when a scan signal voltage is triggered. The storage capacitor includes a first end and a second end coupled to the first transistor and the second transistor, respectively. The third transistor is used for conducting a data signal voltage when the scan signal voltage is triggered. The fourth transistor is used for generating a conducting current based on the data signal voltage when the scan signal voltage is not triggered. The fifth transistor is used for forming a conducting route between the storage capacitor and the fifth transistor. The light-emitting element is used for generating light based on the conducting current of the fourth transistor.

摘要翻译： 像素电路包括耦合到电源电压端的第一晶体管，耦合到接地端的第二晶体管，存储电容器，耦合到数据端的第三晶体管，第四晶体管，耦合到第二晶体管的第五晶体管和 存储电容器的第二端和耦合到第四晶体管的发光元件。 第一晶体管用于响应于使能信号的触发而从电源电压端引导电源电压。 当触发扫描信号电压时，第二晶体管用于从接地端传导接地电压。 存储电容器包括分别耦合到第一晶体管和第二晶体管的第一端和第二端。 当触发扫描信号电压时，第三晶体管用于传导数据信号电压。 当扫描信号电压未被触发时，第四晶体管用于基于数据信号电压产生导通电流。 第五晶体管用于在存储电容器和第五晶体管之间形成导通路径。 发光元件用于基于第四晶体管的导通电流产生光。

公开(公告)号：US08638589B2

公开(公告)日：2014-01-28

申请号：US13366370

申请日：2012-02-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  H01L23/52

CPC分类号： H01L21/28282 ,  G11C16/10 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

摘要翻译： 提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。 存储单元的操作方法包括以下步骤。 在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。 编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是 设置在第二栅极和阱区域之间。