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    Filling high aspect ratio isolation structures with polysilazane based material
    1.
    发明申请
    Filling high aspect ratio isolation structures with polysilazane based material 审中-公开
    用聚硅氮烷基材料填充高纵横比隔离结构

    公开(公告)号：US20050179112A1

    公开(公告)日：2005-08-18

    申请号：US11035392

    申请日：2005-01-12

    申请人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

    发明人： Michael Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth Settlemyer ,  Padraic Shafer

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76229

    摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

    摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    2.
    发明授权
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US06936512B2

    公开(公告)日：2005-08-30

    申请号：US10260085

    申请日：2002-09-27

    申请人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    发明人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。