摘要:
In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising: a) depositing on a first underlayer, a blanket of an aluminum compound containing an electrical short reducing amount of an alloy metal in electrical contact with the underlayer; b) depositing a photoresist and exposing and developing to leave patterns of photoresist on the blanket aluminum compound containing an electrical short reducing amount of an alloy metal; and c) reactive ion etching to obtain an aluminum compound containing an alloy metal line characterized by reduced shorts in amounts less than the aluminum compound without said short reducing amount of alloy metal.
摘要:
A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.
摘要:
A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.
摘要:
Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.
摘要:
In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising:a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill;b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; andc) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.
摘要:
A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
摘要:
A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要:
A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.
摘要:
An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.
摘要:
A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.