Method and apparatus for manufacturing data indexing
    2.
    发明申请
    Method and apparatus for manufacturing data indexing 有权
    用于制造数据索引的方法和装置

    公开(公告)号:US20070179663A1

    公开(公告)日:2007-08-02

    申请号:US11341701

    申请日:2006-01-27

    IPC分类号: G06F19/00

    摘要: A method, apparatus, and a system for generating an index for storing data. A pattern associated with a first set of data is determined. The first set of data is stored. A determination is made as to whether the pattern associated with a second set of data corresponds to the pattern associated with the first set of data. An index associated with the first set of data is correlated to the second set of data in response to determining that the pattern associated with the second set of data corresponds to the pattern associated with the first set of data.

    摘要翻译: 一种用于生成用于存储数据的索引的方法,装置和系统。 确定与第一组数据相关联的模式。 第一组数据被存储。 确定与第二组数据相关联的模式是否对应于与第一组数据相关联的模式。 响应于确定与第二组数据相关联的模式对应于与第一组数据相关联的模式,与第一组数据相关联的索引与第二组数据相关。

    Floating gate process methodology
    3.
    发明授权
    Floating gate process methodology 有权
    浮门过程方法论

    公开(公告)号:US07745236B2

    公开(公告)日:2010-06-29

    申请号:US11614767

    申请日:2006-12-21

    IPC分类号: H01L21/66

    摘要: A method of deprocessing a semiconductor structure is provided. The method involves removing a silicide layer over a second poly layer, an interpoly dielectric layer, a first poly layer, an optionally an oxide layer on a substrate. The method may further involve at least one of removing a second poly layer, removing an interpoly dielectric layer, removing a first poly layer, removing an oxide layer, and removing an unimplanted portion of a substrate. The exposed layer/portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

    摘要翻译: 提供了半导体结构的去加工方法。 该方法包括在第二多晶硅层,多晶硅间介电层,第一多晶硅层,任选的基板上的氧化物层上去除硅化物层。 该方法可以进一步包括去除第二多晶硅层,去除多晶硅绝缘层,去除第一多晶硅层,去除氧化物层以及去除衬底的未被注入的部分中的至少一个。 可以对半导体结构的暴露层/部分进行缺陷和/或其他特性的检查。 检查可以帮助缺陷减少策略,除其他外,应用于新技术坡道,监测基线晶圆启动,客户回报等。

    Copper process methodology
    4.
    发明授权
    Copper process methodology 有权
    铜工艺方法

    公开(公告)号:US07691737B2

    公开(公告)日:2010-04-06

    申请号:US11614770

    申请日:2006-12-21

    IPC分类号: H01L21/4763

    摘要: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

    摘要翻译: 提供了半导体结构的去加工方法。 该方法包括从半导体结构的前面去除一个或多个层间电介质层和一个或多个金属组分。 通过去除层间电介质层和金属部件,可以通过使用检查工具对半导体结构的暴露部分进行缺陷和/或其他特性的检查。 检查可以帮助缺陷减少策略,除其他外,应用于新技术坡道,监测基线晶圆启动,客户回报等。

    COPPER PROCESS METHODOLOGY
    5.
    发明申请
    COPPER PROCESS METHODOLOGY 有权
    铜工艺方法

    公开(公告)号:US20080153185A1

    公开(公告)日:2008-06-26

    申请号:US11614770

    申请日:2006-12-21

    IPC分类号: H01L21/66

    摘要: A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

    摘要翻译: 提供了半导体结构的去加工方法。 该方法包括从半导体结构的前面去除一个或多个层间电介质层和一个或多个金属组分。 通过去除层间电介质层和金属部件,可以通过使用检查工具对半导体结构的暴露部分进行缺陷和/或其他特性的检查。 检查可以帮助缺陷减少策略,除其他外,应用于新技术坡道,监测基线晶圆启动,客户回报等。

    FLOATING GATE PROCESS METHODOLOGY
    6.
    发明申请
    FLOATING GATE PROCESS METHODOLOGY 有权
    浮动门过程方法

    公开(公告)号:US20080153183A1

    公开(公告)日:2008-06-26

    申请号:US11614767

    申请日:2006-12-21

    IPC分类号: H01L21/66

    摘要: A method of deprocessing a semiconductor structure is provided. The method involves removing a silicide layer over a second poly layer, an interpoly dielectric layer, a first poly layer, an optionally an oxide layer on a substrate. The method may further involve at least one of removing a second poly layer, removing an interpoly dielectric layer, removing a first poly layer, removing an oxide layer, and removing an unimplanted portion of a substrate. The exposed layer/portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

    摘要翻译: 提供了半导体结构的去加工方法。 该方法包括在第二多晶硅层,多晶硅间介电层,第一多晶硅层,任选的基板上的氧化物层上去除硅化物层。 该方法可以进一步包括去除第二多晶硅层,去除多晶硅绝缘层,去除第一多晶硅层,去除氧化物层以及去除衬底的未被注入的部分中的至少一个。 可以对半导体结构的暴露层/部分进行缺陷和/或其他特性的检查。 检查可以帮助缺陷减少策略,除其他外,应用于新技术坡道,监测基线晶圆启动,客户回报等。